-mmu_t::mmu_t(char* _mem, size_t _memsz)
- : mem(_mem), memsz(_memsz), proc(NULL)
+mmu_t::mmu_t(sim_t* sim, processor_t* proc)
+ : sim(sim), proc(proc)
const uint16_t* mmu_t::fetch_slow_path(reg_t addr)
{
reg_t paddr = translate(addr, FETCH);
const uint16_t* mmu_t::fetch_slow_path(reg_t addr)
{
reg_t paddr = translate(addr, FETCH);
- else
- throw trap_instruction_access_fault(addr);
- return (const uint16_t*)(mem + paddr);
+ return (const uint16_t*)sim->addr_to_mem(paddr);
+ } else {
+ if (!sim->mmio_load(paddr, sizeof fetch_temp, (uint8_t*)&fetch_temp))
+ throw trap_instruction_access_fault(addr);
+ return &fetch_temp;
+ }
}
void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes)
{
reg_t paddr = translate(addr, LOAD);
}
void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes)
{
reg_t paddr = translate(addr, LOAD);
- if (paddr < memsz) {
- memcpy(bytes, mem + paddr, len);
+ if (sim->addr_is_mem(paddr)) {
+ memcpy(bytes, sim->addr_to_mem(paddr), len);
if (tracer.interested_in_range(paddr, paddr + PGSIZE, LOAD))
tracer.trace(paddr, len, LOAD);
else
refill_tlb(addr, paddr, LOAD);
if (tracer.interested_in_range(paddr, paddr + PGSIZE, LOAD))
tracer.trace(paddr, len, LOAD);
else
refill_tlb(addr, paddr, LOAD);
void mmu_t::store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes)
{
reg_t paddr = translate(addr, STORE);
void mmu_t::store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes)
{
reg_t paddr = translate(addr, STORE);
- if (paddr < memsz) {
- memcpy(mem + paddr, bytes, len);
+ if (sim->addr_is_mem(paddr)) {
+ memcpy(sim->addr_to_mem(paddr), bytes, len);
if (tracer.interested_in_range(paddr, paddr + PGSIZE, STORE))
tracer.trace(paddr, len, STORE);
else
refill_tlb(addr, paddr, STORE);
if (tracer.interested_in_range(paddr, paddr + PGSIZE, STORE))
tracer.trace(paddr, len, STORE);
else
refill_tlb(addr, paddr, STORE);
}
reg_t mmu_t::walk(reg_t addr, access_type type, bool supervisor, bool pum)
}
reg_t mmu_t::walk(reg_t addr, access_type type, bool supervisor, bool pum)