- int levels, ptidxbits, ptesize;
- switch (get_field(proc->get_state()->mstatus, MSTATUS_VM))
- {
- case VM_SV32: levels = 2; ptidxbits = 10; ptesize = 4; break;
- case VM_SV39: levels = 3; ptidxbits = 9; ptesize = 8; break;
- case VM_SV48: levels = 4; ptidxbits = 9; ptesize = 8; break;
- default: abort();
- }
+ reg_t idx = (vaddr >> PGSHIFT) % TLB_ENTRIES;
+ reg_t expected_tag = vaddr >> PGSHIFT;
+
+ if ((tlb_load_tag[idx] & ~TLB_CHECK_TRIGGERS) != expected_tag)
+ tlb_load_tag[idx] = -1;
+ if ((tlb_store_tag[idx] & ~TLB_CHECK_TRIGGERS) != expected_tag)
+ tlb_store_tag[idx] = -1;
+ if ((tlb_insn_tag[idx] & ~TLB_CHECK_TRIGGERS) != expected_tag)
+ tlb_insn_tag[idx] = -1;
+
+ if ((check_triggers_fetch && type == FETCH) ||
+ (check_triggers_load && type == LOAD) ||
+ (check_triggers_store && type == STORE))
+ expected_tag |= TLB_CHECK_TRIGGERS;
+
+ if (type == FETCH) tlb_insn_tag[idx] = expected_tag;
+ else if (type == STORE) tlb_store_tag[idx] = expected_tag;
+ else tlb_load_tag[idx] = expected_tag;
+
+ tlb_entry_t entry = {host_addr - vaddr, paddr - vaddr};
+ tlb_data[idx] = entry;
+ return entry;
+}
+
+reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode)
+{
+ vm_info vm = decode_vm_info(proc->max_xlen, mode, proc->get_state()->satp);
+ if (vm.levels == 0)
+ return addr & ((reg_t(2) << (proc->xlen-1))-1); // zero-extend from xlen
+
+ bool s_mode = mode == PRV_S;
+ bool sum = get_field(proc->state.mstatus, MSTATUS_SUM);
+ bool mxr = get_field(proc->state.mstatus, MSTATUS_MXR);