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Remove redundant U/S mode advertisement
[riscv-isa-sim.git]
/
riscv
/
processor.cc
diff --git
a/riscv/processor.cc
b/riscv/processor.cc
index 1e3573df903e56fc9982bc729baba3a9640f6df1..2dd27496775c45b305ac8135f2f0d8e03bc155f4 100644
(file)
--- a/
riscv/processor.cc
+++ b/
riscv/processor.cc
@@
-22,7
+22,7
@@
processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
bool halt_on_reset)
: debug(false), halt_request(false), sim(sim), ext(NULL), id(id),
processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
bool halt_on_reset)
: debug(false), halt_request(false), sim(sim), ext(NULL), id(id),
- halt_on_reset(halt_on_reset)
+ halt_on_reset(halt_on_reset)
, last_pc(1), executions(1)
{
parse_isa_string(isa);
register_base_instructions();
{
parse_isa_string(isa);
register_base_instructions();
@@
-61,7
+61,7
@@
void processor_t::parse_isa_string(const char* str)
lowercase += std::tolower(*r);
const char* p = lowercase.c_str();
lowercase += std::tolower(*r);
const char* p = lowercase.c_str();
- const char* all_subsets = "imafdc";
+ const char* all_subsets = "imafd
q
c";
max_xlen = 64;
isa = reg_t(2) << 62;
max_xlen = 64;
isa = reg_t(2) << 62;
@@
-74,7
+74,7
@@
void processor_t::parse_isa_string(const char* str)
p += 2;
if (!*p) {
p += 2;
if (!*p) {
- p =
all_subsets
;
+ p =
"imafdc"
;
} else if (*p == 'g') { // treat "G" as "IMAFD"
tmp = std::string("imafd") + (p+1);
p = &tmp[0];
} else if (*p == 'g') { // treat "G" as "IMAFD"
tmp = std::string("imafd") + (p+1);
p = &tmp[0];
@@
-106,9
+106,11
@@
void processor_t::parse_isa_string(const char* str)
if (supports_extension('D') && !supports_extension('F'))
bad_isa_string(str);
if (supports_extension('D') && !supports_extension('F'))
bad_isa_string(str);
- // advertise support for supervisor and user modes
- isa |= 1L << ('s' - 'a');
- isa |= 1L << ('u' - 'a');
+ if (supports_extension('Q') && !supports_extension('D'))
+ bad_isa_string(str);
+
+ if (supports_extension('Q') && max_xlen < 64)
+ bad_isa_string(str);
max_isa = isa;
}
max_isa = isa;
}
@@
-174,7
+176,7
@@
void processor_t::take_interrupt(reg_t pending_interrupts)
if (enabled_interrupts == 0)
enabled_interrupts = pending_interrupts & state.mideleg & -s_enabled;
if (enabled_interrupts == 0)
enabled_interrupts = pending_interrupts & state.mideleg & -s_enabled;
- if (enabled_interrupts)
+ if (
state.dcsr.cause == 0 &&
enabled_interrupts)
throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts));
}
throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts));
}
@@
-187,13
+189,23
@@
static int xlen_to_uxl(int xlen)
abort();
}
abort();
}
-
void processor_t::set
_privilege(reg_t prv)
+
reg_t processor_t::legalize
_privilege(reg_t prv)
{
assert(prv <= PRV_M);
{
assert(prv <= PRV_M);
- if (prv == PRV_H)
- prv = PRV_U;
+
+ if (!supports_extension('U'))
+ return PRV_M;
+
+ if (prv == PRV_H || !supports_extension('S'))
+ return PRV_U;
+
+ return prv;
+}
+
+void processor_t::set_privilege(reg_t prv)
+{
mmu->flush_tlb();
mmu->flush_tlb();
- state.prv =
prv
;
+ state.prv =
legalize_privilege(prv)
;
}
void processor_t::enter_debug_mode(uint8_t cause)
}
void processor_t::enter_debug_mode(uint8_t cause)
@@
-202,7
+214,7
@@
void processor_t::enter_debug_mode(uint8_t cause)
state.dcsr.prv = state.prv;
set_privilege(PRV_M);
state.dpc = state.pc;
state.dcsr.prv = state.prv;
set_privilege(PRV_M);
state.dpc = state.pc;
- state.pc =
debug_rom_entry()
;
+ state.pc =
DEBUG_ROM_ENTRY
;
}
void processor_t::take_trap(trap_t& t, reg_t epc)
}
void processor_t::take_trap(trap_t& t, reg_t epc)
@@
-217,7
+229,7
@@
void processor_t::take_trap(trap_t& t, reg_t epc)
if (state.dcsr.cause) {
if (t.cause() == CAUSE_BREAKPOINT) {
if (state.dcsr.cause) {
if (t.cause() == CAUSE_BREAKPOINT) {
- state.pc =
debug_rom_entry()
;
+ state.pc =
DEBUG_ROM_ENTRY
;
} else {
state.pc = DEBUG_ROM_TVEC;
}
} else {
state.pc = DEBUG_ROM_TVEC;
}
@@
-226,7
+238,6
@@
void processor_t::take_trap(trap_t& t, reg_t epc)
if (t.cause() == CAUSE_BREAKPOINT && (
(state.prv == PRV_M && state.dcsr.ebreakm) ||
if (t.cause() == CAUSE_BREAKPOINT && (
(state.prv == PRV_M && state.dcsr.ebreakm) ||
- (state.prv == PRV_H && state.dcsr.ebreakh) ||
(state.prv == PRV_S && state.dcsr.ebreaks) ||
(state.prv == PRV_U && state.dcsr.ebreaku))) {
enter_debug_mode(DCSR_CAUSE_SWBP);
(state.prv == PRV_S && state.dcsr.ebreaks) ||
(state.prv == PRV_U && state.dcsr.ebreaku))) {
enter_debug_mode(DCSR_CAUSE_SWBP);
@@
-274,9
+285,6
@@
void processor_t::take_trap(trap_t& t, reg_t epc)
void processor_t::disasm(insn_t insn)
{
void processor_t::disasm(insn_t insn)
{
- static uint64_t last_pc = 1, last_bits;
- static uint64_t executions = 1;
-
uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
if (last_pc != state.pc || last_bits != bits) {
if (executions != 1) {
uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
if (last_pc != state.pc || last_bits != bits) {
if (executions != 1) {
@@
-325,11
+333,16
@@
void processor_t::set_csr(int which, reg_t val)
mmu->flush_tlb();
reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
mmu->flush_tlb();
reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
- | MSTATUS_
SPP | MSTATUS_
FS | MSTATUS_MPRV | MSTATUS_SUM
- | MSTATUS_M
PP | MSTATUS_M
XR | MSTATUS_TW | MSTATUS_TVM
+ | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM
+ | MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM
| MSTATUS_TSR | MSTATUS_UXL | MSTATUS_SXL |
(ext ? MSTATUS_XS : 0);
| MSTATUS_TSR | MSTATUS_UXL | MSTATUS_SXL |
(ext ? MSTATUS_XS : 0);
+ reg_t requested_mpp = legalize_privilege(get_field(val, MSTATUS_MPP));
+ state.mstatus = set_field(state.mstatus, MSTATUS_MPP, requested_mpp);
+ if (supports_extension('S'))
+ mask |= MSTATUS_SPP;
+
state.mstatus = (state.mstatus & ~mask) | (val & mask);
bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
state.mstatus = (state.mstatus & ~mask) | (val & mask);
bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
@@
-339,6
+352,7
@@
void processor_t::set_csr(int which, reg_t val)
else
state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
else
state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
+ state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen));
state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen));
state.mstatus = set_field(state.mstatus, MSTATUS_SXL, xlen_to_uxl(max_xlen));
// U-XLEN == S-XLEN == M-XLEN
state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen));
state.mstatus = set_field(state.mstatus, MSTATUS_SXL, xlen_to_uxl(max_xlen));
// U-XLEN == S-XLEN == M-XLEN
@@
-357,10
+371,13
@@
void processor_t::set_csr(int which, reg_t val)
state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
break;
case CSR_MEDELEG: {
state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
break;
case CSR_MEDELEG: {
- reg_t mask = 0;
-#define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
-#include "encoding.h"
-#undef DECLARE_CAUSE
+ reg_t mask =
+ (1 << CAUSE_MISALIGNED_FETCH) |
+ (1 << CAUSE_BREAKPOINT) |
+ (1 << CAUSE_USER_ECALL) |
+ (1 << CAUSE_FETCH_PAGE_FAULT) |
+ (1 << CAUSE_LOAD_PAGE_FAULT) |
+ (1 << CAUSE_STORE_PAGE_FAULT);
state.medeleg = (state.medeleg & ~mask) | (val & mask);
break;
}
state.medeleg = (state.medeleg & ~mask) | (val & mask);
break;
}