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Fix spike-dasm. (#184)
[riscv-isa-sim.git]
/
riscv
/
processor.cc
diff --git
a/riscv/processor.cc
b/riscv/processor.cc
index ce040443977a61faecf7d243dcbedf685574f71c..7a5df901b315c7a5b1642c45415520cdcb659ef3 100644
(file)
--- a/
riscv/processor.cc
+++ b/
riscv/processor.cc
@@
-64,10
+64,10
@@
void processor_t::parse_isa_string(const char* str)
const char* all_subsets = "imafdqc";
max_xlen = 64;
const char* all_subsets = "imafdqc";
max_xlen = 64;
- isa = reg_t(2) << 62;
+
state.m
isa = reg_t(2) << 62;
if (strncmp(p, "rv32", 4) == 0)
if (strncmp(p, "rv32", 4) == 0)
- max_xlen = 32, isa = reg_t(1) << 30, p += 4;
+ max_xlen = 32,
state.m
isa = reg_t(1) << 30, p += 4;
else if (strncmp(p, "rv64", 4) == 0)
p += 4;
else if (strncmp(p, "rv", 2) == 0)
else if (strncmp(p, "rv64", 4) == 0)
p += 4;
else if (strncmp(p, "rv", 2) == 0)
@@
-83,11
+83,11
@@
void processor_t::parse_isa_string(const char* str)
}
isa_string = "rv" + std::to_string(max_xlen) + p;
}
isa_string = "rv" + std::to_string(max_xlen) + p;
- isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
- isa |= 1L << ('u' - 'a'); // advertise support for user mode
+
state.m
isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
+
state.m
isa |= 1L << ('u' - 'a'); // advertise support for user mode
while (*p) {
while (*p) {
- isa |= 1L << (*p - 'a');
+
state.m
isa |= 1L << (*p - 'a');
if (auto next = strchr(all_subsets, *p)) {
all_subsets = next + 1;
if (auto next = strchr(all_subsets, *p)) {
all_subsets = next + 1;
@@
-112,12
+112,13
@@
void processor_t::parse_isa_string(const char* str)
if (supports_extension('Q') && max_xlen < 64)
bad_isa_string(str);
if (supports_extension('Q') && max_xlen < 64)
bad_isa_string(str);
- max_isa = isa;
+ max_isa =
state.m
isa;
}
}
-void state_t::reset()
+void state_t::reset(
reg_t max_isa
)
{
memset(this, 0, sizeof(*this));
{
memset(this, 0, sizeof(*this));
+ misa = max_isa;
prv = PRV_M;
pc = DEFAULT_RSTVEC;
load_reservation = -1;
prv = PRV_M;
pc = DEFAULT_RSTVEC;
load_reservation = -1;
@@
-146,13
+147,16
@@
void processor_t::set_histogram(bool value)
void processor_t::reset()
{
void processor_t::reset()
{
- state.reset();
+ state.reset(
max_isa
);
state.dcsr.halt = halt_on_reset;
halt_on_reset = false;
set_csr(CSR_MSTATUS, state.mstatus);
if (ext)
ext->reset(); // reset the extension
state.dcsr.halt = halt_on_reset;
halt_on_reset = false;
set_csr(CSR_MSTATUS, state.mstatus);
if (ext)
ext->reset(); // reset the extension
+
+ if (sim)
+ sim->proc_reset(id);
}
// Count number of contiguous 0 bits starting from the LSB.
}
// Count number of contiguous 0 bits starting from the LSB.
@@
-458,7
+462,7
@@
void processor_t::set_csr(int which, reg_t val)
mask |= 1L << ('C' - 'A');
mask &= max_isa;
mask |= 1L << ('C' - 'A');
mask &= max_isa;
-
isa = (val & mask) | (
isa & ~mask);
+
state.misa = (val & mask) | (state.m
isa & ~mask);
break;
}
case CSR_TSELECT:
break;
}
case CSR_TSELECT:
@@
-607,7
+611,7
@@
reg_t processor_t::get_csr(int which)
case CSR_MSCRATCH: return state.mscratch;
case CSR_MCAUSE: return state.mcause;
case CSR_MTVAL: return state.mtval;
case CSR_MSCRATCH: return state.mscratch;
case CSR_MCAUSE: return state.mcause;
case CSR_MTVAL: return state.mtval;
- case CSR_MISA: return isa;
+ case CSR_MISA: return
state.m
isa;
case CSR_MARCHID: return 0;
case CSR_MIMPID: return 0;
case CSR_MVENDORID: return 0;
case CSR_MARCHID: return 0;
case CSR_MIMPID: return 0;
case CSR_MVENDORID: return 0;