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Mask medeleg correctly
[riscv-isa-sim.git]
/
riscv
/
processor.cc
diff --git
a/riscv/processor.cc
b/riscv/processor.cc
index ae021657b680819b89b766eca566582731ebf29d..d23c1ea69f7a2b3aa6b61991e91730f50abf06bb 100644
(file)
--- a/
riscv/processor.cc
+++ b/
riscv/processor.cc
@@
-360,10
+360,13
@@
void processor_t::set_csr(int which, reg_t val)
state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
break;
case CSR_MEDELEG: {
state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
break;
case CSR_MEDELEG: {
- reg_t mask = 0;
-#define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
-#include "encoding.h"
-#undef DECLARE_CAUSE
+ reg_t mask =
+ (1 << CAUSE_MISALIGNED_FETCH) |
+ (1 << CAUSE_BREAKPOINT) |
+ (1 << CAUSE_USER_ECALL) |
+ (1 << CAUSE_FETCH_PAGE_FAULT) |
+ (1 << CAUSE_LOAD_PAGE_FAULT) |
+ (1 << CAUSE_STORE_PAGE_FAULT);
state.medeleg = (state.medeleg & ~mask) | (val & mask);
break;
}
state.medeleg = (state.medeleg & ~mask) | (val & mask);
break;
}