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Mask medeleg correctly
[riscv-isa-sim.git]
/
riscv
/
processor.cc
diff --git
a/riscv/processor.cc
b/riscv/processor.cc
index d6da193eba5baef80b0a56402507d8cc51243598..d23c1ea69f7a2b3aa6b61991e91730f50abf06bb 100644
(file)
--- a/
riscv/processor.cc
+++ b/
riscv/processor.cc
@@
-22,7
+22,7
@@
processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
bool halt_on_reset)
: debug(false), halt_request(false), sim(sim), ext(NULL), id(id),
processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
bool halt_on_reset)
: debug(false), halt_request(false), sim(sim), ext(NULL), id(id),
- halt_on_reset(halt_on_reset)
+ halt_on_reset(halt_on_reset)
, last_pc(1), executions(1)
{
parse_isa_string(isa);
register_base_instructions();
{
parse_isa_string(isa);
register_base_instructions();
@@
-61,7
+61,7
@@
void processor_t::parse_isa_string(const char* str)
lowercase += std::tolower(*r);
const char* p = lowercase.c_str();
lowercase += std::tolower(*r);
const char* p = lowercase.c_str();
- const char* all_subsets = "imafdc";
+ const char* all_subsets = "imafd
q
c";
max_xlen = 64;
isa = reg_t(2) << 62;
max_xlen = 64;
isa = reg_t(2) << 62;
@@
-74,7
+74,7
@@
void processor_t::parse_isa_string(const char* str)
p += 2;
if (!*p) {
p += 2;
if (!*p) {
- p =
all_subsets
;
+ p =
"imafdc"
;
} else if (*p == 'g') { // treat "G" as "IMAFD"
tmp = std::string("imafd") + (p+1);
p = &tmp[0];
} else if (*p == 'g') { // treat "G" as "IMAFD"
tmp = std::string("imafd") + (p+1);
p = &tmp[0];
@@
-106,6
+106,12
@@
void processor_t::parse_isa_string(const char* str)
if (supports_extension('D') && !supports_extension('F'))
bad_isa_string(str);
if (supports_extension('D') && !supports_extension('F'))
bad_isa_string(str);
+ if (supports_extension('Q') && !supports_extension('D'))
+ bad_isa_string(str);
+
+ if (supports_extension('Q') && max_xlen < 64)
+ bad_isa_string(str);
+
// advertise support for supervisor and user modes
isa |= 1L << ('s' - 'a');
isa |= 1L << ('u' - 'a');
// advertise support for supervisor and user modes
isa |= 1L << ('s' - 'a');
isa |= 1L << ('u' - 'a');
@@
-174,10
+180,19
@@
void processor_t::take_interrupt(reg_t pending_interrupts)
if (enabled_interrupts == 0)
enabled_interrupts = pending_interrupts & state.mideleg & -s_enabled;
if (enabled_interrupts == 0)
enabled_interrupts = pending_interrupts & state.mideleg & -s_enabled;
- if (enabled_interrupts)
+ if (
state.dcsr.cause == 0 &&
enabled_interrupts)
throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts));
}
throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts));
}
+static int xlen_to_uxl(int xlen)
+{
+ if (xlen == 32)
+ return 1;
+ if (xlen == 64)
+ return 2;
+ abort();
+}
+
void processor_t::set_privilege(reg_t prv)
{
assert(prv <= PRV_M);
void processor_t::set_privilege(reg_t prv)
{
assert(prv <= PRV_M);
@@
-189,12
+204,11
@@
void processor_t::set_privilege(reg_t prv)
void processor_t::enter_debug_mode(uint8_t cause)
{
void processor_t::enter_debug_mode(uint8_t cause)
{
- fprintf(stderr, "Entering debug mode because of cause %d", cause);
state.dcsr.cause = cause;
state.dcsr.prv = state.prv;
set_privilege(PRV_M);
state.dpc = state.pc;
state.dcsr.cause = cause;
state.dcsr.prv = state.prv;
set_privilege(PRV_M);
state.dpc = state.pc;
- state.pc =
debug_rom_entry()
;
+ state.pc =
DEBUG_ROM_ENTRY
;
}
void processor_t::take_trap(trap_t& t, reg_t epc)
}
void processor_t::take_trap(trap_t& t, reg_t epc)
@@
-209,11
+223,9
@@
void processor_t::take_trap(trap_t& t, reg_t epc)
if (state.dcsr.cause) {
if (t.cause() == CAUSE_BREAKPOINT) {
if (state.dcsr.cause) {
if (t.cause() == CAUSE_BREAKPOINT) {
- state.pc = debug_rom_entry();
- fprintf(stderr, "Breakpoint.");
+ state.pc = DEBUG_ROM_ENTRY;
} else {
} else {
- fprintf(stderr, "WE ARE IN DEBUG MODE, DEBUG_ROM_EXCEPTION\n");
- state.pc = DEBUG_ROM_EXCEPTION;
+ state.pc = DEBUG_ROM_TVEC;
}
return;
}
}
return;
}
@@
-268,9
+280,6
@@
void processor_t::take_trap(trap_t& t, reg_t epc)
void processor_t::disasm(insn_t insn)
{
void processor_t::disasm(insn_t insn)
{
- static uint64_t last_pc = 1, last_bits;
- static uint64_t executions = 1;
-
uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
if (last_pc != state.pc || last_bits != bits) {
if (executions != 1) {
uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
if (last_pc != state.pc || last_bits != bits) {
if (executions != 1) {
@@
-321,7
+330,8
@@
void processor_t::set_csr(int which, reg_t val)
reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
| MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM
| MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM
reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
| MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM
| MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM
- | MSTATUS_TSR | (ext ? MSTATUS_XS : 0);
+ | MSTATUS_TSR | MSTATUS_UXL | MSTATUS_SXL |
+ (ext ? MSTATUS_XS : 0);
state.mstatus = (state.mstatus & ~mask) | (val & mask);
state.mstatus = (state.mstatus & ~mask) | (val & mask);
@@
-332,8
+342,9
@@
void processor_t::set_csr(int which, reg_t val)
else
state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
else
state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
- // spike supports the notion of xlen < max_xlen, but current priv spec
- // doesn't provide a mechanism to run RV32 software on an RV64 machine
+ state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen));
+ state.mstatus = set_field(state.mstatus, MSTATUS_SXL, xlen_to_uxl(max_xlen));
+ // U-XLEN == S-XLEN == M-XLEN
xlen = max_xlen;
break;
}
xlen = max_xlen;
break;
}
@@
-349,10
+360,13
@@
void processor_t::set_csr(int which, reg_t val)
state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
break;
case CSR_MEDELEG: {
state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
break;
case CSR_MEDELEG: {
- reg_t mask = 0;
-#define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
-#include "encoding.h"
-#undef DECLARE_CAUSE
+ reg_t mask =
+ (1 << CAUSE_MISALIGNED_FETCH) |
+ (1 << CAUSE_BREAKPOINT) |
+ (1 << CAUSE_USER_ECALL) |
+ (1 << CAUSE_FETCH_PAGE_FAULT) |
+ (1 << CAUSE_LOAD_PAGE_FAULT) |
+ (1 << CAUSE_STORE_PAGE_FAULT);
state.medeleg = (state.medeleg & ~mask) | (val & mask);
break;
}
state.medeleg = (state.medeleg & ~mask) | (val & mask);
break;
}
@@
-534,7
+548,7
@@
reg_t processor_t::get_csr(int which)
case CSR_MCOUNTEREN: return state.mcounteren;
case CSR_SSTATUS: {
reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
case CSR_MCOUNTEREN: return state.mcounteren;
case CSR_SSTATUS: {
reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
- | SSTATUS_XS | SSTATUS_SUM;
+ | SSTATUS_XS | SSTATUS_SUM
| SSTATUS_UXL
;
reg_t sstatus = state.mstatus & mask;
if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
(sstatus & SSTATUS_XS) == SSTATUS_XS)
reg_t sstatus = state.mstatus & mask;
if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
(sstatus & SSTATUS_XS) == SSTATUS_XS)