+class trap_t;
+class extension_t;
+class disassembler_t;
+
+struct insn_desc_t
+{
+ insn_bits_t match;
+ insn_bits_t mask;
+ insn_func_t rv32;
+ insn_func_t rv64;
+};
+
+struct commit_log_reg_t
+{
+ reg_t addr;
+ reg_t data;
+};
+
+typedef struct
+{
+ uint8_t prv;
+ bool step;
+ bool ebreakm;
+ bool ebreakh;
+ bool ebreaks;
+ bool ebreaku;
+ bool halt;
+ uint8_t cause;
+} dcsr_t;
+
+typedef enum
+{
+ ACTION_DEBUG_EXCEPTION = MCONTROL_ACTION_DEBUG_EXCEPTION,
+ ACTION_DEBUG_MODE = MCONTROL_ACTION_DEBUG_MODE,
+ ACTION_TRACE_START = MCONTROL_ACTION_TRACE_START,
+ ACTION_TRACE_STOP = MCONTROL_ACTION_TRACE_STOP,
+ ACTION_TRACE_EMIT = MCONTROL_ACTION_TRACE_EMIT
+} mcontrol_action_t;
+
+typedef enum
+{
+ MATCH_EQUAL = MCONTROL_MATCH_EQUAL,
+ MATCH_NAPOT = MCONTROL_MATCH_NAPOT,
+ MATCH_GE = MCONTROL_MATCH_GE,
+ MATCH_LT = MCONTROL_MATCH_LT,
+ MATCH_MASK_LOW = MCONTROL_MATCH_MASK_LOW,
+ MATCH_MASK_HIGH = MCONTROL_MATCH_MASK_HIGH
+} mcontrol_match_t;
+
+typedef struct
+{
+ uint8_t type;
+ bool dmode;
+ uint8_t maskmax;
+ bool select;
+ bool timing;
+ mcontrol_action_t action;
+ bool chain;
+ mcontrol_match_t match;
+ bool m;
+ bool h;
+ bool s;
+ bool u;
+ bool execute;
+ bool store;
+ bool load;
+} mcontrol_t;
+
+// architectural state of a RISC-V hart
+struct state_t
+{
+ void reset();
+
+ static const int num_triggers = 4;
+
+ reg_t pc;
+ regfile_t<reg_t, NXPR, true> XPR;
+ regfile_t<freg_t, NFPR, false> FPR;
+
+ // control and status registers
+ reg_t prv; // TODO: Can this be an enum instead?
+ reg_t mstatus;
+ reg_t mepc;
+ reg_t mbadaddr;
+ reg_t mscratch;
+ reg_t mtvec;
+ reg_t mcause;
+ reg_t minstret;
+ reg_t mie;
+ reg_t mip;
+ reg_t medeleg;
+ reg_t mideleg;
+ uint32_t mcounteren;
+ uint32_t scounteren;
+ reg_t sepc;
+ reg_t sbadaddr;
+ reg_t sscratch;
+ reg_t stvec;
+ reg_t sptbr;
+ reg_t scause;
+ reg_t dpc;
+ reg_t dscratch;
+ dcsr_t dcsr;
+ reg_t tselect;
+ mcontrol_t mcontrol[num_triggers];
+ reg_t tdata2[num_triggers];
+
+ uint32_t fflags;
+ uint32_t frm;
+ bool serialized; // whether timer CSRs are in a well-defined state
+
+ // When true, execute a single instruction and then enter debug mode. This
+ // can only be set by executing dret.
+ enum {
+ STEP_NONE,
+ STEP_STEPPING,
+ STEP_STEPPED
+ } single_step;
+
+ reg_t load_reservation;
+
+#ifdef RISCV_ENABLE_COMMITLOG
+ commit_log_reg_t log_reg_write;
+ reg_t last_inst_priv;
+#endif
+};
+
+typedef enum {
+ OPERATION_EXECUTE,
+ OPERATION_STORE,
+ OPERATION_LOAD,
+} trigger_operation_t;
+
+// Count number of contiguous 1 bits starting from the LSB.
+static int cto(reg_t val)
+{
+ int res = 0;
+ while ((val & 1) == 1)
+ val >>= 1, res++;
+ return res;
+}