- uint32_t match;
- uint32_t mask;
- insn_func_t rv32;
- insn_func_t rv64;
- };
- unsigned opcode_bits;
- std::multimap<uint32_t, opcode_map_entry_t> opcode_map;
-
- void take_interrupt(); // take a trap if any interrupts are pending
- void set_fsr(uint32_t val); // set the floating-point status register
- void take_trap(reg_t t, bool noisy); // take an exception
- void disasm(insn_t insn, reg_t pc); // disassemble and print an instruction
+ if (state.dcsr.cause)
+ return -1;
+
+ bool chain_ok = true;
+
+ for (unsigned int i = 0; i < state.num_triggers; i++) {
+ if (!chain_ok) {
+ chain_ok |= !state.mcontrol[i].chain;
+ continue;
+ }
+
+ if ((operation == OPERATION_EXECUTE && !state.mcontrol[i].execute) ||
+ (operation == OPERATION_STORE && !state.mcontrol[i].store) ||
+ (operation == OPERATION_LOAD && !state.mcontrol[i].load) ||
+ (state.prv == PRV_M && !state.mcontrol[i].m) ||
+ (state.prv == PRV_H && !state.mcontrol[i].h) ||
+ (state.prv == PRV_S && !state.mcontrol[i].s) ||
+ (state.prv == PRV_U && !state.mcontrol[i].u)) {
+ continue;
+ }
+
+ reg_t value;
+ if (state.mcontrol[i].select) {
+ value = data;
+ } else {
+ value = address;
+ }
+
+ // We need this because in 32-bit mode sometimes the PC bits get sign
+ // extended.
+ if (xlen == 32) {
+ value &= 0xffffffff;
+ }
+
+ switch (state.mcontrol[i].match) {
+ case MATCH_EQUAL:
+ if (value != state.tdata2[i])
+ continue;
+ break;
+ case MATCH_NAPOT:
+ {
+ reg_t mask = ~((1 << cto(state.tdata2[i])) - 1);
+ if ((value & mask) != (state.tdata2[i] & mask))
+ continue;
+ }
+ break;
+ case MATCH_GE:
+ if (value < state.tdata2[i])
+ continue;
+ break;
+ case MATCH_LT:
+ if (value >= state.tdata2[i])
+ continue;
+ break;
+ case MATCH_MASK_LOW:
+ {
+ reg_t mask = state.tdata2[i] >> (xlen/2);
+ if ((value & mask) != (state.tdata2[i] & mask))
+ continue;
+ }
+ break;
+ case MATCH_MASK_HIGH:
+ {
+ reg_t mask = state.tdata2[i] >> (xlen/2);
+ if (((value >> (xlen/2)) & mask) != (state.tdata2[i] & mask))
+ continue;
+ }
+ break;
+ }
+
+ if (!state.mcontrol[i].chain) {
+ return i;
+ }
+ chain_ok = true;
+ }
+ return -1;
+ }
+
+ void trigger_updated();
+
+private:
+ sim_t* sim;
+ mmu_t* mmu; // main memory is always accessed via the mmu
+ extension_t* ext;
+ disassembler_t* disassembler;
+ state_t state;
+ uint32_t id;
+ unsigned max_xlen;
+ unsigned xlen;
+ reg_t isa;
+ reg_t max_isa;
+ std::string isa_string;
+ bool histogram_enabled;
+ bool halt_on_reset;
+
+ std::vector<insn_desc_t> instructions;
+ std::map<reg_t,uint64_t> pc_histogram;
+
+ static const size_t OPCODE_CACHE_SIZE = 8191;
+ insn_desc_t opcode_cache[OPCODE_CACHE_SIZE];
+
+ void take_pending_interrupt() { take_interrupt(state.mip & state.mie); }
+ void take_interrupt(reg_t mask); // take first enabled interrupt in mask
+ void take_trap(trap_t& t, reg_t epc); // take an exception
+ void disasm(insn_t insn); // disassemble and print an instruction
+ int paddr_bits();
+
+ void enter_debug_mode(uint8_t cause);