-
- // terminate the simulation loop after the current iteration
- void stop() { running = false; }
- bool running;
-
- // run each processor for n instructions; interleave instructions are
- // run on a processor before moving on to the next processor.
- // interleave must divide n.
- // if noisy, print out the instructions as they execute.
- void step_all(size_t n, size_t interleave, bool noisy);
+ reg_t start_pc;
+ std::string dts;
+ std::unique_ptr<rom_device_t> boot_rom;
+ std::unique_ptr<clint_t> clint;
+ bus_t bus;
+
+ processor_t* get_core(const std::string& i);
+ void step(size_t n); // step through simulation
+ static const size_t INTERLEAVE = 5000;
+ static const size_t INSNS_PER_RTC_TICK = 100; // 10 MHz clock for 1 BIPS core
+ static const size_t CPU_HZ = 1000000000; // 1GHz CPU
+ size_t current_step;
+ size_t current_proc;
+ bool debug;
+ bool log;
+ bool histogram_enabled; // provide a histogram of PCs
+ remote_bitbang_t* remote_bitbang;
+
+ // memory-mapped I/O routines
+ char* addr_to_mem(reg_t addr);
+ bool mmio_load(reg_t addr, size_t len, uint8_t* bytes);
+ bool mmio_store(reg_t addr, size_t len, const uint8_t* bytes);
+ void make_dtb();