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Add debug module authentication.
[riscv-isa-sim.git]
/
riscv
/
sim.h
diff --git
a/riscv/sim.h
b/riscv/sim.h
index 9372cc1e2d3207d3015e3c43059e8054a9f13acf..6c6e4350702d62b240a42730a20f0b3efbd8f901 100644
(file)
--- a/
riscv/sim.h
+++ b/
riscv/sim.h
@@
-21,7
+21,8
@@
class sim_t : public htif_t
public:
sim_t(const char* isa, size_t _nprocs, bool halted, reg_t start_pc,
std::vector<std::pair<reg_t, mem_t*>> mems,
public:
sim_t(const char* isa, size_t _nprocs, bool halted, reg_t start_pc,
std::vector<std::pair<reg_t, mem_t*>> mems,
- const std::vector<std::string>& args);
+ const std::vector<std::string>& args, const std::vector<int> hartids,
+ unsigned progsize, unsigned max_bus_master_bits, bool require_authentication);
~sim_t();
// run the simulation to completion
~sim_t();
// run the simulation to completion
@@
-37,8
+38,6
@@
public:
processor_t* get_core(size_t i) { return procs.at(i); }
unsigned nprocs() const { return procs.size(); }
processor_t* get_core(size_t i) { return procs.at(i); }
unsigned nprocs() const { return procs.size(); }
- debug_module_t debug_module;
-
private:
std::vector<std::pair<reg_t, mem_t*>> mems;
mmu_t* debug_mmu; // debug port into main memory
private:
std::vector<std::pair<reg_t, mem_t*>> mems;
mmu_t* debug_mmu; // debug port into main memory
@@
-91,6
+90,7
@@
private:
friend class processor_t;
friend class mmu_t;
friend class processor_t;
friend class mmu_t;
+ friend class debug_module_t;
// htif
friend void sim_thread_main(void*);
// htif
friend void sim_thread_main(void*);
@@
-104,6
+104,12
@@
private:
void write_chunk(addr_t taddr, size_t len, const void* src);
size_t chunk_align() { return 8; }
size_t chunk_max_size() { return 8; }
void write_chunk(addr_t taddr, size_t len, const void* src);
size_t chunk_align() { return 8; }
size_t chunk_max_size() { return 8; }
+
+public:
+ // Initialize this after procs, because in debug_module_t::reset() we
+ // enumerate processors, which segfaults if procs hasn't been initialized
+ // yet.
+ debug_module_t debug_module;
};
extern volatile bool ctrlc_pressed;
};
extern volatile bool ctrlc_pressed;