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reorganise twin-predication
[riscv-isa-sim.git]
/
riscv
/
sv.cc
diff --git
a/riscv/sv.cc
b/riscv/sv.cc
index 7f7846ae8d248f4165a93705ce83d8aaa135992b..9cc46507e524b5dfafd3d917762841426bd8dd0e 100644
(file)
--- a/
riscv/sv.cc
+++ b/
riscv/sv.cc
@@
-66,7
+66,7
@@
bool sv_insn_t::sv_check_reg(bool intreg, uint64_t reg)
* of SV. it's "supposed" to "just" be a vectorisation API. it isn't:
* it's quite a bit more.
*/
* of SV. it's "supposed" to "just" be a vectorisation API. it isn't:
* it's quite a bit more.
*/
-uint64_t sv_insn_t::remap(uint64_t reg, bool intreg, int &voffs
, int &newoffs
)
+uint64_t sv_insn_t::remap(uint64_t reg, bool intreg, int &voffs)
{
// okaay so first determine which map to use. intreg is passed
// in (ultimately) from id_regs.py's examination of the use of
{
// okaay so first determine which map to use. intreg is passed
// in (ultimately) from id_regs.py's examination of the use of
@@
-101,10
+101,6
@@
uint64_t sv_insn_t::remap(uint64_t reg, bool intreg, int &voffs, int &newoffs)
// and, at last, we have "parallelism" a la contiguous registers.
reg += voffs; // wheww :)
// and, at last, we have "parallelism" a la contiguous registers.
reg += voffs; // wheww :)
- // however... before returning, we increment the loop-offset for
- // this particular register, so that on the next loop the next
- // contiguous register will be used.
- newoffs = voffs + 1;
return reg;
}
return reg;
}