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add syn_ramstyle "block_ram" attributes and reduce i/d-cache sizes again
[soc.git]
/
src
/
soc
/
experiment
/
dcache.py
diff --git
a/src/soc/experiment/dcache.py
b/src/soc/experiment/dcache.py
index ce1967bd771461f9c2d75c733953d140a37daded..9e75cc01eb59ee42c71ffafdbcec5795c5ff12cb 100644
(file)
--- a/
src/soc/experiment/dcache.py
+++ b/
src/soc/experiment/dcache.py
@@
-747,10
+747,10
@@
class DCache(Elaboratable, DCacheConfig):
if self.microwatt_compat:
# reduce way sizes and num lines
if self.microwatt_compat:
# reduce way sizes and num lines
- super().__init__(NUM_LINES =
8
,
+ super().__init__(NUM_LINES =
4
,
NUM_WAYS = 1,
TLB_NUM_WAYS = 1,
NUM_WAYS = 1,
TLB_NUM_WAYS = 1,
- TLB_SET_SIZE=
16
) # XXX needs device-tree entry
+ TLB_SET_SIZE=
4
) # XXX needs device-tree entry
else:
super().__init__()
else:
super().__init__()