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forgot to pass cix (cache-inhibited) through to LD/ST which was
[soc.git]
/
src
/
soc
/
experiment
/
test
/
test_l0_cache_buffer2.py
diff --git
a/src/soc/experiment/test/test_l0_cache_buffer2.py
b/src/soc/experiment/test/test_l0_cache_buffer2.py
index 066cf431e62577e7d9524c421dcab2153a9f64f8..c331a7b5e5958238a78d5c28f5fdcab873aa351d 100644
(file)
--- a/
src/soc/experiment/test/test_l0_cache_buffer2.py
+++ b/
src/soc/experiment/test/test_l0_cache_buffer2.py
@@
-25,10
+25,10
@@
class TestCachedMemoryPortInterface(PortInterfaceBase):
super().__init__(regwid, addrwid)
self.ldst = LDSTSplitter(32, 48, 4)
super().__init__(regwid, addrwid)
self.ldst = LDSTSplitter(32, 48, 4)
- def set_wr_addr(self, m, addr, mask, misalign, msr, is_dcbz):
+ def set_wr_addr(self, m, addr, mask, misalign, msr, is_dcbz
, is_nc
):
m.d.comb += self.ldst.addr_i.eq(addr)
m.d.comb += self.ldst.addr_i.eq(addr)
- def set_rd_addr(self, m, addr, mask, misalign, msr):
+ def set_rd_addr(self, m, addr, mask, misalign, msr
, is_nc
):
m.d.comb += self.ldst.addr_i.eq(addr)
def set_wr_data(self, m, data, wen):
m.d.comb += self.ldst.addr_i.eq(addr)
def set_wr_data(self, m, data, wen):