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add syn_ramstyle "block_ram" attributes and reduce i/d-cache sizes again
[soc.git]
/
src
/
soc
/
regfile
/
regfile.py
diff --git
a/src/soc/regfile/regfile.py
b/src/soc/regfile/regfile.py
index 07cee2dd6773eb0644da0f9b5216d4f0a1dde7f6..2427a680a94ad5f7dac71b013579dba05bfea27c 100644
(file)
--- a/
src/soc/regfile/regfile.py
+++ b/
src/soc/regfile/regfile.py
@@
-56,7
+56,8
@@
class Register(Elaboratable):
def elaborate(self, platform):
m = Module()
def elaborate(self, platform):
m = Module()
- self.reg = reg = Signal(self.width, name="reg", reset=self.reset)
+ self.reg = reg = Signal(self.width, name="reg", reset=self.reset,
+ attrs={'syn_ramstyle': "block_ram"})
if self.synced:
domain = m.d.sync
if self.synced:
domain = m.d.sync
@@
-290,7
+291,9
@@
class RegFile(Elaboratable):
def elaborate(self, platform):
m = Module()
bsz = int(log(self.width) / log(2))
def elaborate(self, platform):
m = Module()
bsz = int(log(self.width) / log(2))
- regs = Array(Signal(self.width, name="reg") for _ in range(self.depth))
+ regs = Array(Signal(self.width, name="reg",
+ attrs={'syn_ramstyle': "block_ram"}) \
+ for _ in range(self.depth))
# read ports. has write-through detection (returns data written)
for rp in self._rdports:
# read ports. has write-through detection (returns data written)
for rp in self._rdports: