(no commit message)

[libreriscv.git] / 3d_gpu.mdwn

diff --git a/3d_gpu.mdwn b/3d_gpu.mdwn
index 41191640cb3398d51b0e9fc8185da9445eedd887..cc12b5a524ddbc821e43ad23342ffbd915e881ca 100644 (file)
--- a/3d_gpu.mdwn
+++ b/3d_gpu.mdwn
@@ -27,6 +27,8 @@ the cost of product development when it comes to PCB design and layout:
 We can look at larger higher-power ASICs either later or, if funding
 is made available, immediately.
 
+Recent applications to NLNet (Oct 2019) are for a test chip in 180nm, 64 bit, single core dual issue, around 300 to 350mhz.  This will provide the confidence to go to higher geometries, as well as be a commercially viable embedded product in its own right.
+
 See:
 
 * [[shakti/m_class/libre_3d_gpu]]
@@ -81,6 +83,10 @@ Progress:
 * <https://slashdot.org/submission/9750302/nlnet-funds-development-of-a-libre-risc-v-3d-cpu>
 * <https://hardware.slashdot.org/story/19/06/02/0153243/nlnet-funds-development-of-a-libre-risc-v-3d-cpu>
 * <https://www.phoronix.com/forums/forum/hardware/graphics-cards/1104124-libre-risc-v-snags-50k-eur-grant-to-work-on-its-risc-v-3d-gpu-chip/page6>
+* <https://news.ycombinator.com/item?id=21112341>
+* <https://www.reddit.com/r/RISCV/comments/db04j3/libreriscv_3d_cpugpu_seeks_grants_for_ambitious/>
+* <https://hardware.slashdot.org/story/19/09/29/1845252/libre-risc-v-3d-cpugpu-seeks-grants-for-ambitious-expansion>
+* <https://forums.puri.sm/t/risc-v-m-class-effort-and-purism-donation/6528/15>
 
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