add auto-generation of out2 column in SVP64RM

[soc.git] / Makefile

diff --git a/Makefile b/Makefile
index 37d353c14d21749351e06d6163f777ea4476dc2d..28b8f38b1f2e7189b4e62b4c514691424e5957d2 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -13,14 +13,34 @@ mkpinmux:
 
 install: develop mkpinmux
 
+pywriter:
+       python3 src/soc/decoder/pseudo/pywriter.py
+
+svanalysis:
+       python3 libreriscv/openpower/sv_analysis.py
+
 develop:
        python3 setup.py develop # yes, develop, not install
        python3 src/soc/decoder/pseudo/pywriter.py
 
 run_sim: install
-       python3 src/soc/simple/issuer_verilog.py src/soc/litex/florent/libresoc/libresoc.v
+       python3 src/soc/simple/issuer_verilog.py \
+                       src/soc/litex/florent/libresoc/libresoc.v
        python3 src/soc/litex/florent/sim.py --cpu=libresoc
 
+testgpio_run_sim:
+       python3 src/soc/simple/issuer_verilog.py \
+                       src/soc/litex/florent/libresoc/libresoc.v \
+                       --enable-testgpio
+       python3 src/soc/litex/florent/sim.py --cpu=libresoc \
+                       --variant=standardjtagtestgpio
+
+ls180_verilog:
+       python3 src/soc/simple/issuer_verilog.py \
+               --debug=jtag --enable-core --enable-pll \
+               --enable-xics --enable-sram4x4kblock
+                       src/soc/litex/florent/libresoc/libresoc.v
+
 test: install
        python3 setup.py test # could just run nosetest3...