added support for register convention names in debug mode

[riscv-isa-sim.git] / README

diff --git a/README b/README
index 71827bc7d18e0aa06db7683c84f5feae5f8abb50..093bf9fb42381ca653a9a9c0f7632e3cbfeaa31c 100644 (file)
--- a/README
+++ b/README
@@ -65,7 +65,7 @@ To invoke interactive debug mode, launch spike with -d:
 
 To see the contents of a register (0 is for core 0):
 
- : reg 0 14
+ : reg 0 a0
 
 To see the contents of a memory location (physical address in hex):