Update README.md for freg info

[riscv-isa-sim.git] / README.md

diff --git a/README.md b/README.md
index 6f5d0db1f3ab3d8cc85a83d0617252e29d479879..ce078b3589b8e53fa06f7a62d362e3aedf1733f0 100644 (file)
--- a/README.md
+++ b/README.md
@@ -28,12 +28,12 @@ install path, and that the riscv-fesvr package is installed there.
 Compiling and Running a Simple C Program
 -------------------------------------------
 
-Install spike (see Build Steps), riscv-gcc, and riscv-pk.
+Install spike (see Build Steps), riscv-gnu-toolchain, and riscv-pk.
 
 Write a short C program and name it hello.c.  Then, compile it into a RISC-V
 ELF binary named hello:
 
-    $ riscv-gcc -o hello hello.c
+    $ riscv64-unknown-elf-gcc -o hello hello.c
 
 Now you can simulate the program atop the proxy kernel:
 
@@ -64,9 +64,19 @@ To invoke interactive debug mode, launch spike with -d:
 
     $ spike -d pk hello
 
-To see the contents of a register (0 is for core 0):
+To see the contents of an integer register (0 is for core 0):
 
     : reg 0 a0
+    
+To see the contents of a floating point register:
+
+    : fregs 0 ft0
+    
+or:
+  
+    : fregd 0 ft0
+    
+depending upon whether you wish to print the register as single- or double-precision.
 
 To see the contents of a memory location (physical address in hex):