Disasm now translates xor x0,x0,x0 as a machine-generated bubble ("-").

[riscv-isa-sim.git] / config.h.in

diff --git a/config.h.in b/config.h.in
index 28d57d273366a9c2c66dc210710a9e2f30d7e7ce..4ea8c5ed7d98c9d91df668090e3efbc225c6c1fa 100644 (file)
--- a/config.h.in
+++ b/config.h.in
@@ -1,11 +1,17 @@
 /* config.h.in.  Generated from configure.ac by autoheader.  */
 
+/* Define to 1 if you have the `dl' library (-ldl). */
+#undef HAVE_LIBDL
+
 /* Define to 1 if you have the `fesvr' library (-lfesvr). */
 #undef HAVE_LIBFESVR
 
 /* Define to 1 if you have the `pthread' library (-lpthread). */
 #undef HAVE_LIBPTHREAD
 
+/* Define if subproject MCPPBS_SPROJ_NORM is enabled */
+#undef HWACHA_ENABLED
+
 /* Define to the address where bug reports for this package should be sent. */
 #undef PACKAGE_BUGREPORT
 
@@ -30,20 +36,17 @@
 /* Define if 64-bit mode is supported */
 #undef RISCV_ENABLE_64BIT
 
+/* Enable commit log generation */
+#undef RISCV_ENABLE_COMMITLOG
+
 /* Define if floating-point instructions are supported */
 #undef RISCV_ENABLE_FPU
 
-/* Define if instruction compression is supported */
-#undef RISCV_ENABLE_RVC
-
-/* Define if vector processor is supported */
-#undef RISCV_ENABLE_VEC
-
 /* Define if subproject MCPPBS_SPROJ_NORM is enabled */
 #undef SOFTFLOAT_ENABLED
 
 /* Define if subproject MCPPBS_SPROJ_NORM is enabled */
-#undef SOFTFLOAT_RISCV_ENABLED
+#undef SPIKE_ENABLED
 
 /* Define to 1 if you have the ANSI C header files. */
 #undef STDC_HEADERS