Make HW setting of PTE A/D bits optional (by configure arg)

[riscv-isa-sim.git] / config.h.in

diff --git a/config.h.in b/config.h.in
index a4070ff0adba26218f0e45ad320ca023917c53a8..566b1bcc17ef985ec869081924df3db943cd1448 100644 (file)
--- a/config.h.in
+++ b/config.h.in
@@ -66,6 +66,9 @@
 /* Enable commit log generation */
 #undef RISCV_ENABLE_COMMITLOG
 
+/* Enable hardware management of PTE accessed and dirty bits */
+#undef RISCV_ENABLE_DIRTY
+
 /* Enable PC histogram generation */
 #undef RISCV_ENABLE_HISTOGRAM