[xcc] minor performance tweaks

[riscv-isa-sim.git] / config.h.in

diff --git a/config.h.in b/config.h.in
index e59281002c450cc5c6c43bd398972016d709b66c..cf21aff58e97c497ee7cc96ffbc764494b1601df 100644 (file)
--- a/config.h.in
+++ b/config.h.in
@@ -27,6 +27,9 @@
 /* Define if floating-point instructions are supported */
 #undef RISCV_ENABLE_FPU
 
+/* Define if instruction cache simulator is enabled */
+#undef RISCV_ENABLE_ICSIM
+
 /* Define if instruction compression is supported */
 #undef RISCV_ENABLE_RVC