[sim] add disable option for vector

[riscv-isa-sim.git] / config.h.in

diff --git a/config.h.in b/config.h.in
index fb0f56ff607627bb0940bc882b4f485d1aba1331..e59281002c450cc5c6c43bd398972016d709b66c 100644 (file)
--- a/config.h.in
+++ b/config.h.in
@@ -30,6 +30,9 @@
 /* Define if instruction compression is supported */
 #undef RISCV_ENABLE_RVC
 
+/* Define if vector processor is supported */
+#undef RISCV_ENABLE_VEC
+
 /* Define if libopcodes exists */
 #undef RISCV_HAVE_LIBOPCODES