split out cpu_mip to separate module

[rv32.git] / cpu.py

diff --git a/cpu.py b/cpu.py
index 17172c9186b5e8e3e70f7c9bc35fdfe33a4a1bca..7c8d2f39d9fecdb5dc4e66a0a1f33539afdccb0a 100644 (file)
--- a/cpu.py
+++ b/cpu.py
@@ -83,28 +83,8 @@ class MIE:
 
 
 class MIP:
-    def __init__(self, comb, sync):
-        self.comb = comb
-        self.sync = sync
-        self.meip = Signal(name="mip_meip") # TODO: implement ext interrupts
-        self.seip = Signal(name="mip_seip")
-        self.ueip = Signal(name="mip_uiep")
-        self.mtip = Signal(name="mip_mtip") # TODO: implement timer interrupts
-        self.stip = Signal(name="mip_stip")
-        self.msip = Signal(name="mip_stip")
-        self.utip = Signal(name="mip_utip")
-        self.ssip = Signal(name="mip_ssip")
-        self.usip = Signal(name="mip_usip")
-
-        for n in dir(self):
-            if n in ['make', 'comb', 'sync'] or n.startswith("_"):
-                continue
-            self.comb += getattr(self, n).eq(0x0)
-
-    def make(self):
-        return Cat( self.usip, self.ssip, 0, self.msip,
-                    self.utip, self.stip, 0, self.mtip,
-                    self.ueip, self.seip, 0, self.meip, )
+    def __init__(self):
+        self.mip = Signal(32)
 
 
 class M:
@@ -446,7 +426,7 @@ class CPU(Module):
 
         # mip
         c[csr_mip  ] = [
-            csr_output_value.eq(mip.make()),
+            csr_output_value.eq(mip.mip),
             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
                                                   csr_written_value),
         ]
@@ -645,7 +625,12 @@ class CPU(Module):
         mstatus = MStatus(self.comb, self.sync)
         mie = MIE(self.comb, self.sync)
         misa = Misa(self.comb, self.sync)
-        mip = MIP(self.comb, self.sync)
+        mip = MIP()
+
+        mp = Instance("CPUMIP", name="cpu_mip",
+            o_mip = mip.mip)
+
+        self.specials += mp
 
         mii = Instance("CPUMIE", name="cpu_mie",
             o_mie = mie.mie,