Set tval to 0 on traps with no specified tval

[riscv-isa-sim.git] / debug_rom / Makefile

diff --git a/debug_rom/Makefile b/debug_rom/Makefile
index 4e9093cd943173630bdbc027cf4aefc6969f95d8..0a67ba102623b9861ea713ef973a447a4a3cebce 100644 (file)
--- a/debug_rom/Makefile
+++ b/debug_rom/Makefile
@@ -21,4 +21,4 @@ debug_rom:    $(DEPS)
        $(COMPILE) -o $@ $^
 
 clean:
-       rm -f $(ELFS) debug_rom*.raw debug_rom*.h
+       rm -f $(ELFS) debug_rom*.raw debug_rom.h