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Fix 2 trigger corner cases. (#229)
[riscv-isa-sim.git]
/
debug_rom
/
Makefile
diff --git
a/debug_rom/Makefile
b/debug_rom/Makefile
index 0a67ba102623b9861ea713ef973a447a4a3cebce..c5f2205de3bbf38baba4d600342f2277d409d098 100644
(file)
--- a/
debug_rom/Makefile
+++ b/
debug_rom/Makefile
@@
-7,7
+7,7
@@
OBJCOPY = $(RISCV)/bin/riscv64-unknown-elf-objcopy
COMPILE = $(CC) -nostdlib -nostartfiles -I.. -Tlink.ld
ELFS = debug_rom
-DEPS = debug_rom.S link.ld
debug_rom_defines
.h
+DEPS = debug_rom.S link.ld
../riscv/debug_rom_defines.h ../riscv/encoding
.h
all: $(patsubst %,%.h,$(ELFS))