Jump to the correct (temporary) Debug RAM address.

[riscv-isa-sim.git] / debug_rom / debug_rom.S

diff --git a/debug_rom/debug_rom.S b/debug_rom/debug_rom.S
index 230f4b4dacfff1341939247fc95ea09f6bc6da32..16890cf99464540b412d243c792482783d0629ce 100755 (executable)
--- a/debug_rom/debug_rom.S
+++ b/debug_rom/debug_rom.S
@@ -13,7 +13,8 @@
 #define MCPUID                  0xf00
 #define MHARTID                 0xf10
 
-#define DEBUG_RAM               0x400
+# TODO: Should be 0x400
+#define DEBUG_RAM               (-0x400)
 #define DEBUG_RAM_SIZE          64
 
 #define SETHALTNOT              0x100