Use fence.i in Debug ROM.

[riscv-isa-sim.git] / debug_rom / debug_rom.S

diff --git a/debug_rom/debug_rom.S b/debug_rom/debug_rom.S
index e7e99d0b4305994d708d7aa7801d90a2d7e44a64..c164eeb268d4c753af3605d9f8efb5c23e4f7178 100755 (executable)
--- a/debug_rom/debug_rom.S
+++ b/debug_rom/debug_rom.S
@@ -87,6 +87,7 @@ _entry:
 
 jdebugram:
         # Save s1 so that the debug program can use two registers.
+        fence.i
         csrr    s0, CSR_MISA
         bltz    s0, save_not_32
 save_32: