Use new NaN discipline

[riscv-isa-sim.git] / hwacha / insns / vf.h

diff --git a/hwacha/insns/vf.h b/hwacha/insns/vf.h
index 7999428d63589e8018e621a035a3bd57700346fd..395ef1e684c62ff6e2997eaba5467dd1de6e1179 100644 (file)
--- a/hwacha/insns/vf.h
+++ b/hwacha/insns/vf.h
@@ -10,7 +10,7 @@ vf_loop:
   if (VF_PC & 3)
     h->take_exception(HWACHA_CAUSE_VF_MISALIGNED_FETCH, VF_PC);
 
-  insn_t ut_insn = p->get_mmu()->load_insn(VF_PC).insn.insn;
+  insn_t ut_insn = p->get_mmu()->load_insn(VF_PC).insn;
 
   bool matched = false;
 
@@ -21,7 +21,6 @@ vf_loop:
       matched = true; \
     }
   #include "opcodes_hwacha_ut.h"
-  #include "opcodes_hwacha_ut_half.h"
   #undef DECLARE_INSN
 
   if (!matched)
@@ -31,7 +30,7 @@ vf_loop:
     if (h->vf_active())
       goto vf_loop;
   } else {
-    fprintf(stderr, "vf block: 0x%016" PRIx64 " (0x%08" PRIx32 ") %s\n",
+    fprintf(stderr, "vf block: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
       VF_PC, ut_insn.bits(), h->get_ut_disassembler()->disassemble(ut_insn).c_str());
     if (h->vf_active())
       npc = pc;