add hwacha exception support

[riscv-isa-sim.git] / hwacha / insns / vsetcfg.h

diff --git a/hwacha/insns/vsetcfg.h b/hwacha/insns/vsetcfg.h
index a5fd9594dea82c96499efc4c71b6bd1ceefd08f5..c18812db50aeeee1f8f6cdb03d945250c6695eb4 100644 (file)
--- a/hwacha/insns/vsetcfg.h
+++ b/hwacha/insns/vsetcfg.h
@@ -1,7 +1,9 @@
 uint32_t nxpr = (XS1 & 0x3f) + (insn.i_imm() & 0x3f);
 uint32_t nfpr = ((XS1 >> 6) & 0x3f) + ((insn.i_imm() >> 6) & 0x3f);
-// YUNSUP FIXME
-// raise trap when nxpr/nfpr is larger than possible
+if (nxpr > 32)
+  h->take_exception(HWACHA_CAUSE_ILLEGAL_CFG, 0);
+if (nfpr > 32)
+  h->take_exception(HWACHA_CAUSE_ILLEGAL_CFG, 1);
 WRITE_NXPR(nxpr);
 WRITE_NFPR(nfpr);
 uint32_t maxvl;