Merge pull request #117 from riscv/multicore_debug

[riscv-isa-sim.git] / riscv / cachesim.cc

diff --git a/riscv/cachesim.cc b/riscv/cachesim.cc
index 9a1118708987fadc18abfbc627cb4d9f46d730e1..90ab5be3d9ff168db3cbc769e3ac550d6b2b41ea 100644 (file)
--- a/riscv/cachesim.cc
+++ b/riscv/cachesim.cc
@@ -45,7 +45,7 @@ void cache_sim_t::init()
     help();
 
   idx_shift = 0;
-  for (size_t x = linesz; x; x >>= 1)
+  for (size_t x = linesz; x>1; x >>= 1)
     idx_shift++;
 
   tags = new uint64_t[sets*ways]();