Fix debug reset.

[riscv-isa-sim.git] / riscv / cachesim.h

diff --git a/riscv/cachesim.h b/riscv/cachesim.h
index a52900785feb330c64c47bc05607f5fd31443477..d597f792cd4ca0e3f86bc2522af03636fda05d6f 100644 (file)
--- a/riscv/cachesim.h
+++ b/riscv/cachesim.h
@@ -97,13 +97,13 @@ class icache_sim_t : public cache_memtracer_t
 {
  public:
   icache_sim_t(const char* config) : cache_memtracer_t(config, "I$") {}
-  bool interested_in_range(uint64_t begin, uint64_t end, bool store, bool fetch)
+  bool interested_in_range(uint64_t begin, uint64_t end, access_type type)
   {
-    return fetch;
+    return type == FETCH;
   }
-  void trace(uint64_t addr, size_t bytes, bool store, bool fetch)
+  void trace(uint64_t addr, size_t bytes, access_type type)
   {
-    if (fetch) cache->access(addr, bytes, false);
+    if (type == FETCH) cache->access(addr, bytes, false);
   }
 };
 
@@ -111,13 +111,13 @@ class dcache_sim_t : public cache_memtracer_t
 {
  public:
   dcache_sim_t(const char* config) : cache_memtracer_t(config, "D$") {}
-  bool interested_in_range(uint64_t begin, uint64_t end, bool store, bool fetch)
+  bool interested_in_range(uint64_t begin, uint64_t end, access_type type)
   {
-    return !fetch;
+    return type == LOAD || type == STORE;
   }
-  void trace(uint64_t addr, size_t bytes, bool store, bool fetch)
+  void trace(uint64_t addr, size_t bytes, access_type type)
   {
-    if (!fetch) cache->access(addr, bytes, store);
+    if (type == LOAD || type == STORE) cache->access(addr, bytes, type == STORE);
   }
 };