bool debug_module_data_t::load(reg_t addr, size_t len, uint8_t* bytes)
{
- D(fprintf(stderr, "debug_module_data_t load 0x%lx bytes at 0x%lx\n", len,
- addr));
-
if (addr + len < sizeof(data)) {
memcpy(bytes, data + addr, len);
return true;
///////////////////////// debug_module_t
-debug_module_t::debug_module_t(sim_t *sim) : sim(sim)
+debug_module_t::debug_module_t(sim_t *sim) : sim(sim),
+ next_action(jal(ZERO, 0)),
+ action_executed(false)
{
dmcontrol = {0};
dmcontrol.version = 1;
halted[i] = false;
}
- for (unsigned i = 0; i < progsize; i++) {
- ibuf[i] = 0;
- }
-
+ memset(program_buffer, 0, sizeof(program_buffer));
}
void debug_module_t::reset()
bool debug_module_t::load(reg_t addr, size_t len, uint8_t* bytes)
{
- D(fprintf(stderr, "load 0x%lx bytes at 0x%lx\n",
- len, addr));
addr = DEBUG_START + addr;
if (addr >= DEBUG_ROM_ENTRY &&
addr < DEBUG_ROM_ENTRY + DEBUG_ROM_ENTRY_SIZE) {
- halted[(addr - DEBUG_ROM_ENTRY) / 4] = true;
- memcpy(bytes, debug_rom_entry + addr - DEBUG_ROM_ENTRY, len);
if (read32(debug_rom_entry, dmcontrol.hartsel) == jal(ZERO, 0)) {
// We're here in an infinite loop. That means that whatever abstract
// command has complete.
abstractcs.busy = false;
}
+
+ action_executed = true;
+
+ halted[(addr - DEBUG_ROM_ENTRY) / 4] = true;
+ memcpy(bytes, debug_rom_entry + addr - DEBUG_ROM_ENTRY, len);
return true;
}
- // Restore the jump-to-self loop.
- write32(debug_rom_entry, dmcontrol.hartsel, jal(ZERO, 0));
+ if (action_executed) {
+ // Restore the jump-to-self loop.
+ write32(debug_rom_entry, dmcontrol.hartsel, next_action);
+ next_action = jal(ZERO, 0);
+ action_executed = false;
+ }
if (addr >= DEBUG_ROM_CODE &&
addr < DEBUG_ROM_CODE + DEBUG_ROM_CODE_SIZE) {
+
+ if (read32(debug_rom_code, 0) == dret()) {
+ abstractcs.busy = false;
+ halted[dmcontrol.hartsel] = false;
+ }
+
memcpy(bytes, debug_rom_code + addr - DEBUG_ROM_CODE, len);
return true;
}
+ if (addr >= DEBUG_RAM_START && addr < DEBUG_RAM_END) {
+ memcpy(bytes, program_buffer + addr - DEBUG_RAM_START, len);
+ return true;
+ }
+
if (addr >= DEBUG_ROM_EXCEPTION &&
addr < DEBUG_ROM_EXCEPTION + DEBUG_ROM_EXCEPTION_SIZE) {
memcpy(bytes, debug_rom_exception + addr - DEBUG_ROM_EXCEPTION, len);
{
addr = DEBUG_START + addr;
+ if (addr >= DEBUG_RAM_START && addr < DEBUG_RAM_END) {
+ memcpy(program_buffer + addr - DEBUG_RAM_START, bytes, len);
+ return true;
+ }
+
fprintf(stderr, "ERROR: invalid store to debug module: %zd bytes at 0x%016"
PRIx64 "\n", len, addr);
return false;
uint32_t result = 0;
D(fprintf(stderr, "dmi_read(0x%x) -> ", address));
if (address >= DMI_DATA0 && address < DMI_DATA0 + abstractcs.datacount) {
- result = dmdata.read32(4 * (address - DMI_DATA0));
+ unsigned i = address - DMI_DATA0;
+ result = dmdata.read32(4 * i);
+
+ if (abstractcs.busy && abstractcs.cmderr == abstractcs.CMDERR_NONE) {
+ abstractcs.cmderr = abstractcs.CMDERR_BUSY;
+ }
+
+ bool autoexec = false;
+ switch (i) {
+ case 0: autoexec = abstractcs.autoexec0; break;
+ case 1: autoexec = abstractcs.autoexec1; break;
+ case 2: autoexec = abstractcs.autoexec2; break;
+ case 3: autoexec = abstractcs.autoexec3; break;
+ case 4: autoexec = abstractcs.autoexec4; break;
+ case 5: autoexec = abstractcs.autoexec5; break;
+ case 6: autoexec = abstractcs.autoexec6; break;
+ case 7: autoexec = abstractcs.autoexec7; break;
+ }
+ if (autoexec) {
+ perform_abstract_command();
+ }
} else if (address >= DMI_IBUF0 && address < DMI_IBUF0 + progsize) {
- result = ibuf[address - DMI_IBUF0];
+ result = read32(program_buffer, address - DMI_IBUF0);
} else {
switch (address) {
case DMI_DMCONTROL:
return true;
}
-bool debug_module_t::perform_abstract_command(uint32_t command)
+bool debug_module_t::perform_abstract_command()
{
if (abstractcs.cmderr != abstractcs.CMDERR_NONE)
return true;
abstractcs.cmderr = abstractcs.CMDERR_NOTSUP;
return true;
}
- write32(debug_rom_code, 1, ebreak());
+ if (get_field(command, AC_ACCESS_REGISTER_POSTEXEC)) {
+ write32(debug_rom_code, 1, jal(ZERO, DEBUG_RAM_START - DEBUG_ROM_CODE - 4));
+ } else {
+ write32(debug_rom_code, 1, ebreak());
+ }
+
+ if (get_field(command, AC_ACCESS_REGISTER_PREEXEC)) {
+ write32(debug_rom_entry, dmcontrol.hartsel,
+ jal(ZERO, DEBUG_RAM_START - (DEBUG_ROM_ENTRY + 4 * dmcontrol.hartsel)));
+ next_action =
+ jal(ZERO, DEBUG_ROM_CODE - (DEBUG_ROM_ENTRY + 4 * dmcontrol.hartsel));
+ } else {
+ write32(debug_rom_entry, dmcontrol.hartsel,
+ jal(ZERO, DEBUG_ROM_CODE - (DEBUG_ROM_ENTRY + 4 * dmcontrol.hartsel)));
+ }
- write32(debug_rom_entry, dmcontrol.hartsel,
- jal(ZERO, DEBUG_ROM_CODE - (DEBUG_ROM_ENTRY + 4 * dmcontrol.hartsel)));
write32(debug_rom_exception, dmcontrol.hartsel,
jal(ZERO, (DEBUG_ROM_ENTRY + 4 * dmcontrol.hartsel) - DEBUG_ROM_EXCEPTION));
abstractcs.busy = true;
{
D(fprintf(stderr, "dmi_write(0x%x, 0x%x)\n", address, value));
if (address >= DMI_DATA0 && address < DMI_DATA0 + abstractcs.datacount) {
- dmdata.write32(4 * (address - DMI_DATA0), value);
+ unsigned i = address - DMI_DATA0;
+ dmdata.write32(4 * i, value);
+
+ if (abstractcs.busy && abstractcs.cmderr == abstractcs.CMDERR_NONE) {
+ abstractcs.cmderr = abstractcs.CMDERR_BUSY;
+ }
+
+ bool autoexec = false;
+ switch (i) {
+ case 0: autoexec = abstractcs.autoexec0; break;
+ case 1: autoexec = abstractcs.autoexec1; break;
+ case 2: autoexec = abstractcs.autoexec2; break;
+ case 3: autoexec = abstractcs.autoexec3; break;
+ case 4: autoexec = abstractcs.autoexec4; break;
+ case 5: autoexec = abstractcs.autoexec5; break;
+ case 6: autoexec = abstractcs.autoexec6; break;
+ case 7: autoexec = abstractcs.autoexec7; break;
+ }
+ if (autoexec) {
+ perform_abstract_command();
+ }
return true;
+
} else if (address >= DMI_IBUF0 && address < DMI_IBUF0 + progsize) {
- ibuf[address - DMI_IBUF0] = value;
+ write32(program_buffer, address - DMI_IBUF0, value);
return true;
} else {
switch (address) {
dmcontrol.dmactive = get_field(value, DMI_DMCONTROL_DMACTIVE);
if (dmcontrol.dmactive) {
dmcontrol.haltreq = get_field(value, DMI_DMCONTROL_HALTREQ);
+ dmcontrol.resumereq = get_field(value, DMI_DMCONTROL_RESUMEREQ);
dmcontrol.reset = get_field(value, DMI_DMCONTROL_RESET);
dmcontrol.hartsel = get_field(value, DMI_DMCONTROL_HARTSEL);
} else {
processor_t *proc = current_proc();
if (proc) {
proc->halt_request = dmcontrol.haltreq;
+ if (dmcontrol.resumereq) {
+ write32(debug_rom_code, 0, dret());
+ write32(debug_rom_entry, dmcontrol.hartsel,
+ jal(ZERO, DEBUG_ROM_CODE - (DEBUG_ROM_ENTRY + 4 * dmcontrol.hartsel)));
+ abstractcs.busy = true;
+ }
}
}
return true;
case DMI_COMMAND:
- return perform_abstract_command(value);
+ command = value;
+ return perform_abstract_command();
case DMI_ABSTRACTCS:
abstractcs.autoexec7 = get_field(value, DMI_ABSTRACTCS_AUTOEXEC7);
if (get_field(value, DMI_ABSTRACTCS_CMDERR) == abstractcs.CMDERR_NONE) {
abstractcs.cmderr = abstractcs.CMDERR_NONE;
}
- break;
+ return true;
}
}
return false;
projects / riscv-isa-sim.git / blobdiff