Set tval to 0 on traps with no specified tval

[riscv-isa-sim.git] / riscv / debug_module.cc

diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc
index 8d73f07d0ab3585642b88f1ef56c764bebeb0347..985cbbdc30f610b75d15a9ad4b418591595b5c70 100644 (file)
--- a/riscv/debug_module.cc
+++ b/riscv/debug_module.cc
@@ -447,6 +447,7 @@ bool debug_module_t::dmi_write(unsigned address, uint32_t value)
           if (dmcontrol.dmactive) {
             dmcontrol.haltreq = get_field(value, DMI_DMCONTROL_HALTREQ);
             dmcontrol.resumereq = get_field(value, DMI_DMCONTROL_RESUMEREQ);
+            dmcontrol.hartreset = get_field(value, DMI_DMCONTROL_HARTRESET);
             dmcontrol.ndmreset = get_field(value, DMI_DMCONTROL_NDMRESET);
             dmcontrol.hartsel = get_field(value, DMI_DMCONTROL_HARTSEL);
           } else {