Fix 2 trigger corner cases. (#229)

[riscv-isa-sim.git] / riscv / debug_module.h

diff --git a/riscv/debug_module.h b/riscv/debug_module.h
index 50107fcf562e520dc0da3d4664bd7736d9e76b23..3aa3f0f7d724c8afa7b4c467cb7f4496a8914d0f 100644 (file)
--- a/riscv/debug_module.h
+++ b/riscv/debug_module.h
@@ -116,6 +116,8 @@ class debug_module_t : public abstract_device_t
     static const unsigned debug_abstract_size = 5;
     unsigned debug_abstract_start;
 
+    // We only support 1024 harts currently. More requires at least resizing
+    // the arrays below, and their corresponding special memory regions.
     static const unsigned hartsellen = 10;
 
     sim_t *sim;