debug: Checkpoint which somewhat works with OpenOCD v13, but still has some bugs.

[riscv-isa-sim.git] / riscv / debug_module.h

diff --git a/riscv/debug_module.h b/riscv/debug_module.h
index eaaf06e9fab79a4f72d5eba2ca4764e9e51053ca..d3398ea69e1ae995fe322b2b3b55ff402cc55b0c 100644 (file)
--- a/riscv/debug_module.h
+++ b/riscv/debug_module.h
@@ -11,55 +11,50 @@ class sim_t;
 typedef struct {
   bool haltreq;
   bool resumereq;
-  enum {
-    HARTSTATUS_HALTED,
-    HARTSTATUS_RUNNING,
-    HARTSTATUS_UNAVAILABLE,
-    HARTSTATUS_NOTEXIST
-  } hartstatus;
   unsigned hartsel;
   bool hartreset;
   bool dmactive;
-  bool reset;
-  bool authenticated;
-  bool authbusy;
-  unsigned version;
+  bool ndmreset;
 } dmcontrol_t;
 
 typedef struct {
-  bool autoexec7;
-  bool autoexec6;
-  bool autoexec5;
-  bool autoexec4;
-  bool autoexec3;
-  bool autoexec2;
-  bool autoexec1;
-  bool autoexec0;
-  enum {
+  bool allnonexistant;
+  bool anynonexistant;
+  bool allunavail;
+  bool anyunavail;
+  bool allrunning;
+  bool anyrunning;
+  bool allhalted;
+  bool anyhalted;
+  bool allresumeack;
+  bool anyresumeack;
+  bool authenticated;
+  bool authbusy;
+  bool cfgstrvalid;
+  unsigned versionhi;
+  unsigned versionlo;
+} dmstatus_t;
+
+typedef enum cmderr {
     CMDERR_NONE = 0,
     CMDERR_BUSY = 1,
     CMDERR_NOTSUP = 2,
     CMDERR_EXCEPTION = 3,
     CMDERR_HALTRESUME = 4,
-    CMDERR_OTHER = 7
-  } cmderr;
+    CMDERR_OTHER = 7  
+} cmderr_t;
+
+typedef struct {
   bool busy;
   unsigned datacount;
+  unsigned progsize;
+  cmderr_t cmderr;
 } abstractcs_t;
 
-class debug_module_data_t : public abstract_device_t
-{
-  public:
-    debug_module_data_t();
-
-    bool load(reg_t addr, size_t len, uint8_t* bytes);
-    bool store(reg_t addr, size_t len, const uint8_t* bytes);
-
-    uint32_t read32(reg_t addr) const;
-    void write32(reg_t addr, uint32_t value);
-
-    uint8_t data[DEBUG_EXCHANGE_SIZE];
-};
+typedef struct {
+  unsigned autoexecprogbuf;
+  unsigned autoexecdata;
+} abstractauto_t;
 
 class debug_module_t : public abstract_device_t
 {
@@ -82,22 +77,22 @@ class debug_module_t : public abstract_device_t
 
     sim_t *sim;
 
-    uint8_t debug_rom_entry[DEBUG_ROM_ENTRY_SIZE];
-    uint8_t debug_rom_code[DEBUG_ROM_CODE_SIZE];
-    uint8_t debug_rom_exception[DEBUG_ROM_EXCEPTION_SIZE];
+    uint8_t debug_rom_whereto[4];
+    uint8_t debug_rom_abstract[4*2];
     uint8_t program_buffer[progsize * 4];
+    uint8_t dmdata[DEBUG_DATA_SIZE];
+    
     bool halted[1024];
-    debug_module_data_t dmdata;
-    // Instruction that will be placed at the current hart's ROM entry address
-    // after the current action has completed.
-    uint32_t next_action;
-    bool action_executed;
+    bool resumeack[1024];
+    uint8_t debug_rom_flags[1024];
 
     void write32(uint8_t *rom, unsigned int index, uint32_t value);
     uint32_t read32(uint8_t *rom, unsigned int index);
 
     dmcontrol_t dmcontrol;
+    dmstatus_t dmstatus;
     abstractcs_t abstractcs;
+    abstractauto_t abstractauto;
     uint32_t command;
 
     processor_t *current_proc() const;