[sim] integrated SoftFloat-3 with ISA sim; removed SoftFloat-2b

[riscv-isa-sim.git] / riscv / decode.h

diff --git a/riscv/decode.h b/riscv/decode.h
index 424ad7fdfe85fbe6ec6f9c063e0f74238f7634ae..1b631ae0526017182ca781a901af258fd7a0d8b1 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -38,20 +38,21 @@ const int BIGIMM_BITS = 20;
 #define SR_IM    0x000000000000FF00ULL
 #define SR_ZERO  ~(SR_ET | SR_PS | SR_S | SR_EF | SR_UX | SR_KX | SR_IM)
 
-#define FP_RD_NE 0
-#define FP_RD_0  1
-#define FP_RD_UP 2
-#define FP_RD_DN 3
+#define FP_RD_NE  0
+#define FP_RD_0   1
+#define FP_RD_DN  2
+#define FP_RD_UP  3
+#define FP_RD_NMM 4
 #define FSR_RD_SHIFT 10
-#define FSR_RD   (0x3 << FSR_RD_SHIFT)
+#define FSR_RD   (0x7 << FSR_RD_SHIFT)
 
-#define FPEXC_NV 0x10
-#define FPEXC_OF 0x08
-#define FPEXC_UF 0x04
-#define FPEXC_DZ 0x02
 #define FPEXC_NX 0x01
+#define FPEXC_UF 0x02
+#define FPEXC_OF 0x04
+#define FPEXC_DZ 0x02
+#define FPEXC_NV 0x10
 
-#define FSR_AEXC_SHIFT 5
+#define FSR_AEXC_SHIFT 0
 #define FSR_NVA  (FPEXC_NV << FSR_AEXC_SHIFT)
 #define FSR_OFA  (FPEXC_OF << FSR_AEXC_SHIFT)
 #define FSR_UFA  (FPEXC_UF << FSR_AEXC_SHIFT)
@@ -59,15 +60,7 @@ const int BIGIMM_BITS = 20;
 #define FSR_NXA  (FPEXC_NX << FSR_AEXC_SHIFT)
 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
 
-#define FSR_CEXC_SHIFT 0
-#define FSR_NVC  (FPEXC_NV << FSR_AEXC_SHIFT)
-#define FSR_OFC  (FPEXC_OF << FSR_AEXC_SHIFT)
-#define FSR_UFC  (FPEXC_UF << FSR_AEXC_SHIFT)
-#define FSR_DZC  (FPEXC_DZ << FSR_AEXC_SHIFT)
-#define FSR_NXC  (FPEXC_NX << FSR_AEXC_SHIFT)
-#define FSR_CEXC (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
-
-#define FSR_ZERO ~(FSR_RD | FSR_AEXC | FSR_CEXC)
+#define FSR_ZERO ~(FSR_RD | FSR_AEXC)
 
 // note: bit fields are in little-endian order
 struct itype_t
@@ -143,10 +136,9 @@ union insn_t
 #define require64 if(gprlen != 64) throw trap_illegal_instruction
 #define require_fp if(!(sr & SR_EF)) throw trap_fp_disabled
 #define cmp_trunc(reg) (reg_t(reg) << (64-gprlen))
-#define set_fp_exceptions ({ set_fsr((fsr & ~FSR_CEXC) | \
-                                (float_exception_flags << FSR_AEXC_SHIFT) | \
-                                (float_exception_flags << FSR_CEXC_SHIFT)); \
-                             float_exception_flags = 0; })
+#define set_fp_exceptions ({ set_fsr(fsr | \
+                                (softfloat_exceptionFlags << FSR_AEXC_SHIFT)); \
+                             softfloat_exceptionFlags = 0; })
 
 static inline sreg_t sext32(int32_t arg)
 {