[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / decode.h

diff --git a/riscv/decode.h b/riscv/decode.h
index 59ca87a117f8a9094132b8cc1585fb7d639b5fe5..2078e58ae2cc028e1b5959a9f04ca0ce2abf4a62 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -143,30 +143,29 @@ union insn_t
   uint32_t bits;
 };
 
-#if 0
 #include <stdio.h>
-class trace_writeback
+class do_writeback
 {
 public:
-  trace_writeback(reg_t* _rf, int _rd) : rf(_rf), rd(_rd) {}
+  do_writeback(reg_t* _rf, int _rd) : rf(_rf), rd(_rd) {}
 
-  reg_t operator = (reg_t rhs)
+  const do_writeback& operator = (reg_t rhs)
   {
+#if 0
     printf("R[%x] <= %llx\n",rd,(long long)rhs);
+#endif
     rf[rd] = rhs;
-    return rhs;
+    rf[0] = 0;
+    return *this;
   }
 
+  operator reg_t() { return rf[rd]; }
+
 private:
   reg_t* rf;
   int rd;
 };
 
-#define do_writeback(rf,rd) trace_writeback(rf,rd)
-#else
-#define do_writeback(rf,rd) rf[rd]
-#endif
-
 #define throw_illegal_instruction \
   ({ if (utmode) throw trap_vector_illegal_instruction; \
      else throw trap_illegal_instruction; })
@@ -212,6 +211,20 @@ private:
 #define sext_xprlen(x) ((sreg_t(x) << (64-xprlen)) >> (64-xprlen))
 #define zext_xprlen(x) ((reg_t(x) << (64-xprlen)) >> (64-xprlen))
 
+#ifndef RISCV_ENABLE_RVC
+# define set_pc(x) \
+  do { if((x) & (sizeof(insn_t)-1)) \
+       { badvaddr = (x); throw trap_instruction_address_misaligned; } \
+       npc = (x); \
+     } while(0)
+#else
+# define set_pc(x) \
+  do { if((x) & ((sr & SR_EC) ? 1 : 3)) \
+       { badvaddr = (x); throw trap_instruction_address_misaligned; } \
+       npc = (x); \
+     } while(0)
+#endif
+
 // RVC stuff
 
 #define INSN_IS_RVC(x) (((x) & 0x3) < 0x3)