Simplify RV32 comparisons

[riscv-isa-sim.git] / riscv / decode.h

diff --git a/riscv/decode.h b/riscv/decode.h
index 5d304a123a7c404e75ec3d43d8562114c1de4ff3..55f03ffcdfb6d7260cf35d11603b2042a952f19d 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -180,7 +180,6 @@ private:
 #endif
 #define require_accelerator if (unlikely((STATE.mstatus & MSTATUS_XS) == 0)) throw trap_illegal_instruction()
 
-#define cmp_trunc(reg) (reg_t(reg) << (64-xlen))
 #define set_fp_exceptions ({ STATE.fflags |= softfloat_exceptionFlags; \
                              softfloat_exceptionFlags = 0; })