+// See LICENSE for license details.
+
#ifndef _RISCV_DECODE_H
#define _RISCV_DECODE_H
+#if (-1 != ~0) || ((-1 >> 1) != -1)
+# error spike requires a two''s-complement c++ implementation
+#endif
+
#define __STDC_LIMIT_MACROS
#include <stdint.h>
-
+#include <string.h>
+#include "pcr.h"
#include "config.h"
+#include "common.h"
+#include <cinttypes>
typedef int int128_t __attribute__((mode(TI)));
typedef unsigned int uint128_t __attribute__((mode(TI)));
typedef uint64_t reg_t;
typedef uint64_t freg_t;
-const int OPCODE_BITS = 7;
-
-const int XPRID_BITS = 5;
-const int NXPR = 1 << XPRID_BITS;
-
-const int FPR_BITS = 64;
-const int FPRID_BITS = 5;
-const int NFPR = 1 << FPRID_BITS;
-
-const int IMM_BITS = 12;
-const int IMMLO_BITS = 7;
-const int TARGET_BITS = 25;
-const int FUNCT_BITS = 3;
-const int FUNCTR_BITS = 7;
-const int FFUNCT_BITS = 2;
-const int RM_BITS = 3;
-const int BIGIMM_BITS = 20;
-const int BRANCH_ALIGN_BITS = 1;
-const int JUMP_ALIGN_BITS = 1;
-
-#define SR_ET 0x0000000000000001ULL
-#define SR_EF 0x0000000000000002ULL
-#define SR_EV 0x0000000000000004ULL
-#define SR_EC 0x0000000000000008ULL
-#define SR_PS 0x0000000000000010ULL
-#define SR_S 0x0000000000000020ULL
-#define SR_UX 0x0000000000000040ULL
-#define SR_SX 0x0000000000000080ULL
-#define SR_IM 0x000000000000FF00ULL
-#define SR_VM 0x0000000000010000ULL
-#define SR_ZERO ~(SR_ET|SR_EF|SR_EV|SR_EC|SR_PS|SR_S|SR_UX|SR_SX|SR_IM|SR_VM)
-#define SR_IM_SHIFT 8
-#define IPI_IRQ 5
-#define TIMER_IRQ 7
-
-#define CAUSE_EXCCODE 0x000000FF
-#define CAUSE_IP 0x0000FF00
-#define CAUSE_EXCCODE_SHIFT 0
-#define CAUSE_IP_SHIFT 8
+const int NXPR = 32;
+const int NFPR = 32;
#define FP_RD_NE 0
#define FP_RD_0 1
#define FSR_ZERO ~(FSR_RD | FSR_AEXC)
-// note: bit fields are in little-endian order
-struct itype_t
-{
- unsigned opcode : OPCODE_BITS;
- unsigned funct : FUNCT_BITS;
- signed imm12 : IMM_BITS;
- unsigned rs1 : XPRID_BITS;
- unsigned rd : XPRID_BITS;
-};
-
-struct btype_t
-{
- unsigned opcode : OPCODE_BITS;
- unsigned funct : FUNCT_BITS;
- unsigned immlo : IMMLO_BITS;
- unsigned rs2 : XPRID_BITS;
- unsigned rs1 : XPRID_BITS;
- signed immhi : IMM_BITS-IMMLO_BITS;
-};
-
-struct jtype_t
-{
- unsigned jump_opcode : OPCODE_BITS;
- signed target : TARGET_BITS;
-};
-
-struct rtype_t
-{
- unsigned opcode : OPCODE_BITS;
- unsigned funct : FUNCT_BITS;
- unsigned functr : FUNCTR_BITS;
- unsigned rs2 : XPRID_BITS;
- unsigned rs1 : XPRID_BITS;
- unsigned rd : XPRID_BITS;
-};
-
-struct ltype_t
-{
- unsigned opcode : OPCODE_BITS;
- unsigned bigimm : BIGIMM_BITS;
- unsigned rd : XPRID_BITS;
-};
-
-struct ftype_t
+class insn_t
{
- unsigned opcode : OPCODE_BITS;
- unsigned ffunct : FFUNCT_BITS;
- unsigned rm : RM_BITS;
- unsigned rs3 : FPRID_BITS;
- unsigned rs2 : FPRID_BITS;
- unsigned rs1 : FPRID_BITS;
- unsigned rd : FPRID_BITS;
-};
-
-union insn_t
-{
- itype_t itype;
- jtype_t jtype;
- rtype_t rtype;
- btype_t btype;
- ltype_t ltype;
- ftype_t ftype;
- uint32_t bits;
+public:
+ uint32_t bits() { return b; }
+ reg_t i_imm() { return int64_t(int32_t(b) >> 20); }
+ reg_t s_imm() { return x(7, 5) | (x(25, 7) << 5) | (imm_sign() << 12); }
+ reg_t sb_imm() { return (x(8, 4) << 1) | (x(25,6) << 5) | (x(7,1) << 11) | (imm_sign() << 12); }
+ reg_t u_imm() { return int64_t(int32_t(b) >> 12 << 12); }
+ reg_t uj_imm() { return (x(21, 10) << 1) | (x(20, 1) << 11) | (x(12, 8) << 12) | (imm_sign() << 20); }
+ uint32_t rd() { return x(7, 5); }
+ uint32_t rs1() { return x(15, 5); }
+ uint32_t rs2() { return x(20, 5); }
+ uint32_t rs3() { return x(27, 5); }
+ uint32_t rm() { return x(12, 3); }
+private:
+ uint32_t b;
+ reg_t x(int lo, int len) { return b << (32-lo-len) >> (32-len); }
+ reg_t imm_sign() { return int64_t(int32_t(b) >> 31); }
};
-#include <stdio.h>
-class do_writeback
+template <class T, size_t N, bool zero_reg>
+class regfile_t
{
public:
- do_writeback(reg_t* _rf, int _rd) : rf(_rf), rd(_rd) {}
-
- const do_writeback& operator = (reg_t rhs)
+ void reset()
{
-#if 0
- printf("R[%x] <= %llx\n",rd,(long long)rhs);
-#endif
- rf[rd] = rhs;
- rf[0] = 0;
- return *this;
+ memset(data, 0, sizeof(data));
+ }
+ void write(size_t i, T value)
+ {
+ data[i] = value;
+ }
+ const T& operator [] (size_t i) const
+ {
+ if (zero_reg)
+ const_cast<T&>(data[0]) = 0;
+ return data[i];
}
-
- operator reg_t() { return rf[rd]; }
-
private:
- reg_t* rf;
- int rd;
+ T data[N];
};
-#define throw_illegal_instruction \
- ({ if (utmode) throw trap_vector_illegal_instruction; \
- else throw trap_illegal_instruction; })
-
// helpful macros, etc
-#define RS1 XPR[insn.rtype.rs1]
-#define RS2 XPR[insn.rtype.rs2]
-#define RD do_writeback(XPR,insn.rtype.rd)
-#define RA do_writeback(XPR,1)
-#define FRS1 FPR[insn.ftype.rs1]
-#define FRS2 FPR[insn.ftype.rs2]
-#define FRS3 FPR[insn.ftype.rs3]
-#define FRD FPR[insn.ftype.rd]
-#define BIGIMM insn.ltype.bigimm
-#define SIMM insn.itype.imm12
-#define BIMM ((signed)insn.btype.immlo | (insn.btype.immhi << IMMLO_BITS))
-#define SHAMT (insn.itype.imm12 & 0x3F)
-#define SHAMTW (insn.itype.imm12 & 0x1F)
-#define TARGET insn.jtype.target
-#define BRANCH_TARGET (pc + (BIMM << BRANCH_ALIGN_BITS))
-#define JUMP_TARGET (pc + (TARGET << JUMP_ALIGN_BITS))
-#define RM ({ int rm = insn.ftype.rm; \
- if(rm == 7) rm = (fsr & FSR_RD) >> FSR_RD_SHIFT; \
- if(rm > 4) throw_illegal_instruction; \
+#define MMU (*p->get_mmu())
+#define RS1 p->get_state()->XPR[insn.rs1()]
+#define RS2 p->get_state()->XPR[insn.rs2()]
+#define WRITE_RD(value) p->get_state()->XPR.write(insn.rd(), value)
+
+#ifdef RISCV_ENABLE_COMMITLOG
+ #undef WRITE_RD
+ #define WRITE_RD(value) ({ \
+ bool in_spvr = p->get_state()->sr & SR_S; \
+ reg_t wdata = value; /* value is a func with side-effects */ \
+ if (!in_spvr) \
+ fprintf(stderr, "x%u 0x%016" PRIx64, insn.rd(), ((uint64_t) wdata)); \
+ p->get_state()->XPR.write(insn.rd(), wdata); \
+ })
+#endif
+
+#define FRS1 p->get_state()->FPR[insn.rs1()]
+#define FRS2 p->get_state()->FPR[insn.rs2()]
+#define FRS3 p->get_state()->FPR[insn.rs3()]
+#define WRITE_FRD(value) p->get_state()->FPR.write(insn.rd(), value)
+
+#ifdef RISCV_ENABLE_COMMITLOG
+ #undef WRITE_FRD
+ #define WRITE_FRD(value) ({ \
+ bool in_spvr = p->get_state()->sr & SR_S; \
+ freg_t wdata = value; /* value is a func with side-effects */ \
+ if (!in_spvr) \
+ fprintf(stderr, "f%u 0x%016" PRIx64, insn.rd(), ((uint64_t) wdata)); \
+ p->get_state()->FPR.write(insn.rd(), wdata); \
+ })
+#endif
+
+
+
+#define SHAMT (insn.i_imm() & 0x3F)
+#define BRANCH_TARGET (pc + insn.sb_imm())
+#define JUMP_TARGET (pc + insn.uj_imm())
+#define RM ({ int rm = insn.rm(); \
+ if(rm == 7) rm = (p->get_state()->fsr & FSR_RD) >> FSR_RD_SHIFT; \
+ if(rm > 4) throw trap_illegal_instruction(); \
rm; })
-#define require_supervisor if(unlikely(!(sr & SR_S))) throw trap_privileged_instruction
#define xpr64 (xprlen == 64)
-#define require_xpr64 if(unlikely(!xpr64)) throw_illegal_instruction
-#define require_xpr32 if(unlikely(xpr64)) throw_illegal_instruction
-#define require_fp if(unlikely(!(sr & SR_EF))) throw trap_fp_disabled
-#define require_vector \
- ({ if(!(sr & SR_EV)) throw trap_vector_disabled; \
- else if (!utmode && (vecbanks_count < 3)) throw trap_vector_bank; \
- })
+
+#define require_supervisor if(unlikely(!(p->get_state()->sr & SR_S))) throw trap_privileged_instruction()
+#define require_xpr64 if(unlikely(!xpr64)) throw trap_illegal_instruction()
+#define require_xpr32 if(unlikely(xpr64)) throw trap_illegal_instruction()
+#ifndef RISCV_ENABLE_FPU
+# define require_fp throw trap_illegal_instruction()
+#else
+# define require_fp if(unlikely(!(p->get_state()->sr & SR_EF))) throw trap_fp_disabled()
+#endif
+
#define cmp_trunc(reg) (reg_t(reg) << (64-xprlen))
-#define set_fp_exceptions ({ set_fsr(fsr | \
+#define set_fp_exceptions ({ p->set_fsr(p->get_state()->fsr | \
(softfloat_exceptionFlags << FSR_AEXC_SHIFT)); \
softfloat_exceptionFlags = 0; })
#define sext32(x) ((sreg_t)(int32_t)(x))
#define zext32(x) ((reg_t)(uint32_t)(x))
-#define sext_xprlen(x) ((sreg_t(x) << (64-xprlen)) >> (64-xprlen))
-#define zext_xprlen(x) ((reg_t(x) << (64-xprlen)) >> (64-xprlen))
-
-#ifndef RISCV_ENABLE_RVC
-# define set_pc(x) \
- do { if((x) & (sizeof(insn_t)-1)) \
- { badvaddr = (x); throw trap_instruction_address_misaligned; } \
+#define sext_xprlen(x) (((sreg_t)(x) << (64-xprlen)) >> (64-xprlen))
+#define zext_xprlen(x) (((reg_t)(x) << (64-xprlen)) >> (64-xprlen))
+
+#define insn_length(x) \
+ (((x) & 0x03) < 0x03 ? 2 : \
+ ((x) & 0x1f) < 0x1f ? 4 : \
+ ((x) & 0x3f) < 0x3f ? 6 : \
+ 8)
+
+#define set_pc(x) \
+ do { if ((x) & 3 /* For now... */) \
+ throw trap_instruction_address_misaligned(); \
npc = (x); \
} while(0)
-#else
-# define set_pc(x) \
- do { if((x) & ((sr & SR_EC) ? 1 : 3)) \
- { badvaddr = (x); throw trap_instruction_address_misaligned; } \
- npc = (x); \
- } while(0)
-#endif
-
-// RVC stuff
-
-#define INSN_IS_RVC(x) (((x) & 0x3) < 0x3)
-#define insn_length(x) (INSN_IS_RVC(x) ? 2 : 4)
-#define require_rvc if(!(sr & SR_EC)) throw_illegal_instruction
-
-#define CRD_REGNUM ((insn.bits >> 5) & 0x1f)
-#define CRD do_writeback(XPR, CRD_REGNUM)
-#define CRS1 XPR[(insn.bits >> 10) & 0x1f]
-#define CRS2 XPR[(insn.bits >> 5) & 0x1f]
-#define CIMM6 ((int32_t)((insn.bits >> 10) & 0x3f) << 26 >> 26)
-#define CIMM5U ((insn.bits >> 5) & 0x1f)
-#define CIMM5 ((int32_t)CIMM5U << 27 >> 27)
-#define CIMM10 ((int32_t)((insn.bits >> 5) & 0x3ff) << 22 >> 22)
-#define CBRANCH_TARGET (pc + (CIMM5 << BRANCH_ALIGN_BITS))
-#define CJUMP_TARGET (pc + (CIMM10 << JUMP_ALIGN_BITS))
-
-static const int rvc_rs1_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 7 };
-#define rvc_rd_regmap rvc_rs1_regmap
-#define rvc_rs2b_regmap rvc_rs1_regmap
-static const int rvc_rs2_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 0 };
-#define CRDS XPR[rvc_rd_regmap[(insn.bits >> 13) & 0x7]]
-#define FCRDS FPR[rvc_rd_regmap[(insn.bits >> 13) & 0x7]]
-#define CRS1S XPR[rvc_rs1_regmap[(insn.bits >> 10) & 0x7]]
-#define CRS2S XPR[rvc_rs2_regmap[(insn.bits >> 13) & 0x7]]
-#define CRS2BS XPR[rvc_rs2b_regmap[(insn.bits >> 5) & 0x7]]
-#define FCRS2S FPR[rvc_rs2_regmap[(insn.bits >> 13) & 0x7]]
-
-// vector stuff
-#define VL vl
-
-#define UT_RS1(idx) uts[idx]->XPR[insn.rtype.rs1]
-#define UT_RS2(idx) uts[idx]->XPR[insn.rtype.rs2]
-#define UT_RD(idx) do_writeback(uts[idx]->XPR,insn.rtype.rd)
-#define UT_RA(idx) do_writeback(uts[idx]->XPR,1)
-#define UT_FRS1(idx) uts[idx]->FPR[insn.ftype.rs1]
-#define UT_FRS2(idx) uts[idx]->FPR[insn.ftype.rs2]
-#define UT_FRS3(idx) uts[idx]->FPR[insn.ftype.rs3]
-#define UT_FRD(idx) uts[idx]->FPR[insn.ftype.rd]
-#define UT_RM(idx) ((insn.ftype.rm != 7) ? insn.ftype.rm : \
- ((uts[idx]->fsr & FSR_RD) >> FSR_RD_SHIFT))
-
-#define UT_LOOP_START for (int i=0;i<VL; i++) {
-#define UT_LOOP_END }
-#define UT_LOOP_RS1 UT_RS1(i)
-#define UT_LOOP_RS2 UT_RS2(i)
-#define UT_LOOP_RD UT_RD(i)
-#define UT_LOOP_RA UT_RA(i)
-#define UT_LOOP_FRS1 UT_FRS1(i)
-#define UT_LOOP_FRS2 UT_FRS2(i)
-#define UT_LOOP_FRS3 UT_FRS3(i)
-#define UT_LOOP_FRD UT_FRD(i)
-#define UT_LOOP_RM UT_RM(i)
-
-#define VEC_LOAD(dst, func, inc) \
- reg_t addr = RS1; \
- UT_LOOP_START \
- UT_LOOP_##dst = mmu.func(addr); \
- addr += inc; \
- UT_LOOP_END
-
-#define VEC_STORE(src, func, inc) \
- reg_t addr = RS1; \
- UT_LOOP_START \
- mmu.func(addr, UT_LOOP_##src); \
- addr += inc; \
- UT_LOOP_END
-
-enum vt_command_t
-{
- vt_command_stop,
-};
#endif
projects / riscv-isa-sim.git / blobdiff