Added commit logging (--enable-commitlog). Also fixed disasm bug.

[riscv-isa-sim.git] / riscv / decode.h

diff --git a/riscv/decode.h b/riscv/decode.h
index e1a6b7401f8913f2126567429187874d3269c438..7cf7eacc913abb30d71ffbcb9d79b2a299f17ff2 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -3,12 +3,17 @@
 #ifndef _RISCV_DECODE_H
 #define _RISCV_DECODE_H
 
+#if (-1 != ~0) || ((-1 >> 1) != -1)
+# error spike requires a two''s-complement c++ implementation
+#endif
+
 #define __STDC_LIMIT_MACROS
 #include <stdint.h>
 #include <string.h>
 #include "pcr.h"
 #include "config.h"
 #include "common.h"
+#include <cinttypes>
 
 typedef int int128_t __attribute__((mode(TI)));
 typedef unsigned int uint128_t __attribute__((mode(TI)));
@@ -49,38 +54,22 @@ class insn_t
 {
 public:
   uint32_t bits() { return b; }
-  reg_t i_imm() { return x(11, 11) | (imm_sign() << 11); }
-  reg_t s_imm() { return x(11, 6) | (x(27, 5) << 6) | (imm_sign() << 11); }
-  reg_t sb_imm() { return (x(12, 5) << 1) | (x(27, 5) << 6) | (x(11, 1) << 11) | (imm_sign() << 12); }
-  reg_t u_imm() { return (x(22, 5) << 12) | (x(7, 3) << 17) | (x(11, 11) << 20) | (imm_sign() << 31); }
-  reg_t uj_imm() { return (x(12, 10) << 1) | (x(11, 1) << 11) | (x(22, 5) << 12) | (x(7, 3) << 17) | (imm_sign() << 20); }
-  uint32_t rd() { return x(27, 5); }
-  uint32_t rs1() { return x(22, 5); }
-  uint32_t rs2() { return x(17, 5); }
-  uint32_t rs3() { return x(12, 5); }
-  uint32_t rm() { return x(9, 3); }
+  reg_t i_imm() { return int64_t(int32_t(b) >> 20); }
+  reg_t s_imm() { return x(7, 5) | (x(25, 7) << 5) | (imm_sign() << 12); }
+  reg_t sb_imm() { return (x(8, 4) << 1) | (x(25,6) << 5) | (x(7,1) << 11) | (imm_sign() << 12); }
+  reg_t u_imm() { return int64_t(int32_t(b) >> 12 << 12); }
+  reg_t uj_imm() { return (x(21, 10) << 1) | (x(20, 1) << 11) | (x(12, 8) << 12) | (imm_sign() << 20); }
+  uint32_t rd() { return x(7, 5); }
+  uint32_t rs1() { return x(15, 5); }
+  uint32_t rs2() { return x(20, 5); }
+  uint32_t rs3() { return x(27, 5); }
+  uint32_t rm() { return x(12, 3); }
 private:
   uint32_t b;
   reg_t x(int lo, int len) { return b << (32-lo-len) >> (32-len); }
-  reg_t imm_sign() { return -x(10, 1); }
+  reg_t imm_sign() { return int64_t(int32_t(b) >> 31); }
 };
 
-template <class T>
-class write_port_t
-{
-public:
-  write_port_t(T& _t) : t(_t) {}
-  T& operator = (const T& rhs)
-  {
-    return t = rhs;
-  }
-  operator T()
-  {
-    return t;
-  }
-private:
-  T& t;
-};
 template <class T, size_t N, bool zero_reg>
 class regfile_t
 {
@@ -89,11 +78,9 @@ public:
   {
     memset(data, 0, sizeof(data));
   }
-  write_port_t<T> write_port(size_t i)
+  void write(size_t i, T value)
   {
-    if (zero_reg)
-      const_cast<T&>(data[0]) = 0;
-    return write_port_t<T>(data[i]);
+    data[i] = value;
   }
   const T& operator [] (size_t i) const
   {
@@ -109,11 +96,37 @@ private:
 #define MMU (*p->get_mmu())
 #define RS1 p->get_state()->XPR[insn.rs1()]
 #define RS2 p->get_state()->XPR[insn.rs2()]
-#define RD p->get_state()->XPR.write_port(insn.rd())
+#define WRITE_RD(value) p->get_state()->XPR.write(insn.rd(), value)
+
+#ifdef RISCV_ENABLE_COMMITLOG
+  #undef WRITE_RD 
+  #define WRITE_RD(value) ({ \
+        bool in_spvr = p->get_state()->sr & SR_S; \
+        reg_t wdata = value; /* value is a func with side-effects */ \
+        if (!in_spvr) \
+          fprintf(stderr, "x%u 0x%016" PRIx64, insn.rd(), ((uint64_t) wdata)); \
+        p->get_state()->XPR.write(insn.rd(), wdata); \
+      })
+#endif
+
 #define FRS1 p->get_state()->FPR[insn.rs1()]
 #define FRS2 p->get_state()->FPR[insn.rs2()]
 #define FRS3 p->get_state()->FPR[insn.rs3()]
-#define FRD p->get_state()->FPR.write_port(insn.rd())
+#define WRITE_FRD(value) p->get_state()->FPR.write(insn.rd(), value)
+ 
+#ifdef RISCV_ENABLE_COMMITLOG
+  #undef WRITE_FRD 
+  #define WRITE_FRD(value) ({ \
+        bool in_spvr = p->get_state()->sr & SR_S; \
+        freg_t wdata = value; /* value is a func with side-effects */ \
+        if (!in_spvr) \
+          fprintf(stderr, "f%u 0x%016" PRIx64, insn.rd(), ((uint64_t) wdata)); \
+        p->get_state()->FPR.write(insn.rd(), wdata); \
+      })
+#endif
+ 
+
+
 #define SHAMT (insn.i_imm() & 0x3F)
 #define BRANCH_TARGET (pc + insn.sb_imm())
 #define JUMP_TARGET (pc + insn.uj_imm())