Set tval to 0 on traps with no specified tval

[riscv-isa-sim.git] / riscv / decode.h

diff --git a/riscv/decode.h b/riscv/decode.h
index 45dd3c43a83b7bd80c72604e69de5d35ccce614f..7f5effc741933b9a3b97fba5f54992ce2dac477f 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -139,12 +139,12 @@ private:
 #else
 # define WRITE_REG(reg, value) ({ \
     reg_t wdata = (value); /* value may have side effects */ \
-    STATE.log_reg_write = (commit_log_reg_t){(reg) << 1, wdata}; \
+    STATE.log_reg_write = (commit_log_reg_t){(reg) << 1, {wdata, 0}}; \
     STATE.XPR.write(reg, wdata); \
   })
 # define WRITE_FREG(reg, value) ({ \
     freg_t wdata = freg(value); /* value may have side effects */ \
-    STATE.log_reg_write = (commit_log_reg_t){((reg) << 1) | 1, wdata.v}; \
+    STATE.log_reg_write = (commit_log_reg_t){((reg) << 1) | 1, wdata}; \
     DO_WRITE_FREG(reg, wdata); \
   })
 #endif