[xcc,pk,sim,opcodes] added first RVC instruction

[riscv-isa-sim.git] / riscv / decode.h

diff --git a/riscv/decode.h b/riscv/decode.h
index d0b92ddc470f7ff8f858b50b6bb4e56cccd827a5..8d96ab9da02e319f54ddcf3e5819cb81990f16d2 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -34,13 +34,15 @@ const int BRANCH_ALIGN_BITS = 1;
 const int JUMP_ALIGN_BITS = 1;
 
 #define SR_ET    0x0000000000000001ULL
+#define SR_EF    0x0000000000000002ULL
 #define SR_PS    0x0000000000000004ULL
 #define SR_S     0x0000000000000008ULL
-#define SR_EF    0x0000000000000010ULL
-#define SR_UX    0x0000000000000020ULL
-#define SR_SX    0x0000000000000040ULL
+#define SR_UX    0x0000000000000010ULL
+#define SR_SX    0x0000000000000020ULL
+#define SR_UC    0x0000000000000040ULL
+#define SR_SC    0x0000000000000080ULL
 #define SR_IM    0x000000000000FF00ULL
-#define SR_ZERO  ~(SR_ET | SR_PS | SR_S | SR_EF | SR_UX | SR_SX | SR_IM)
+#define SR_ZERO  ~(SR_ET|SR_EF|SR_PS|SR_S|SR_UX|SR_SX|SR_UC|SR_SC|SR_IM)
 #define SR_IM_SHIFT 8
 #define TIMER_IRQ 7
 
@@ -193,11 +195,16 @@ private:
                                (softfloat_exceptionFlags << FSR_AEXC_SHIFT)); \
                              softfloat_exceptionFlags = 0; })
 
-static inline sreg_t sext32(int32_t arg)
-{
-  return arg;
-}
+#define rvc_mode ((sr & SR_S) ? (sr & SR_SC) : (sr & SR_UC))
+#define require_rvc if(!rvc_mode) throw trap_illegal_instruction
 
+#define sext32(x) ((sreg_t)(int32_t)(x))
+#define insn_length(x) (((x).bits & 0x3) < 0x3 ? 2 : 4)
 #define sext_xprlen(x) ((sreg_t(x) << (64-xprlen)) >> (64-xprlen))
 
+// RVC stuff
+
+#define CRD do_writeback(XPR,(insn.bits >> 5) & 0x1f)
+#define CIMM6 ((int32_t)((insn.bits >> 10) & 0x3f) << 26 >> 26)
+
 #endif