+// See LICENSE for license details.
+
#ifndef _RISCV_DECODE_H
#define _RISCV_DECODE_H
-#define __STDC_LIMIT_MACROS
-#include <stdint.h>
-#include "common.h"
-#include "config.h"
+#if (-1 != ~0) || ((-1 >> 1) != -1)
+# error spike requires a two''s-complement c++ implementation
+#endif
-typedef int int128_t __attribute__((mode(TI)));
-typedef unsigned int uint128_t __attribute__((mode(TI)));
+#include <cstdint>
+#include <string.h>
+#include <strings.h>
+#include "encoding.h"
+#include "config.h"
+#include "common.h"
+#include <cinttypes>
typedef int64_t sreg_t;
typedef uint64_t reg_t;
typedef uint64_t freg_t;
-const int OPCODE_BITS = 7;
-
-const int XPRID_BITS = 5;
-const int NXPR = 1 << XPRID_BITS;
-
-const int FPR_BITS = 64;
-const int FPRID_BITS = 5;
-const int NFPR = 1 << FPRID_BITS;
-
-const int IMM_BITS = 12;
-const int IMMLO_BITS = 7;
-const int TARGET_BITS = 25;
-const int FUNCT_BITS = 3;
-const int FUNCTR_BITS = 7;
-const int FFUNCT_BITS = 2;
-const int RM_BITS = 3;
-const int BIGIMM_BITS = 20;
-const int BRANCH_ALIGN_BITS = 1;
-const int JUMP_ALIGN_BITS = 1;
-
-#define SR_ET 0x0000000000000001ULL
-#define SR_EF 0x0000000000000002ULL
-#define SR_EV 0x0000000000000004ULL
-#define SR_EC 0x0000000000000008ULL
-#define SR_PS 0x0000000000000010ULL
-#define SR_S 0x0000000000000020ULL
-#define SR_UX 0x0000000000000040ULL
-#define SR_SX 0x0000000000000080ULL
-#define SR_IM 0x000000000000FF00ULL
-#define SR_VM 0x0000000000010000ULL
-#define SR_ZERO ~(SR_ET|SR_EF|SR_EV|SR_EC|SR_PS|SR_S|SR_UX|SR_SX|SR_IM|SR_VM)
-#define SR_IM_SHIFT 8
-#define IPI_IRQ 5
-#define TIMER_IRQ 7
-
-#define CAUSE_EXCCODE 0x000000FF
-#define CAUSE_IP 0x0000FF00
-#define CAUSE_EXCCODE_SHIFT 0
-#define CAUSE_IP_SHIFT 8
+const int NXPR = 32;
+const int NFPR = 32;
#define FP_RD_NE 0
#define FP_RD_0 1
#define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT)
#define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
-#define FSR_ZERO ~(FSR_RD | FSR_AEXC)
-
-// note: bit fields are in little-endian order
-struct itype_t
-{
- unsigned opcode : OPCODE_BITS;
- unsigned funct : FUNCT_BITS;
- signed imm12 : IMM_BITS;
- unsigned rs1 : XPRID_BITS;
- unsigned rd : XPRID_BITS;
-};
-
-struct btype_t
-{
- unsigned opcode : OPCODE_BITS;
- unsigned funct : FUNCT_BITS;
- unsigned immlo : IMMLO_BITS;
- unsigned rs2 : XPRID_BITS;
- unsigned rs1 : XPRID_BITS;
- signed immhi : IMM_BITS-IMMLO_BITS;
-};
-
-struct jtype_t
-{
- unsigned jump_opcode : OPCODE_BITS;
- signed target : TARGET_BITS;
-};
-
-struct rtype_t
-{
- unsigned opcode : OPCODE_BITS;
- unsigned funct : FUNCT_BITS;
- unsigned functr : FUNCTR_BITS;
- unsigned rs2 : XPRID_BITS;
- unsigned rs1 : XPRID_BITS;
- unsigned rd : XPRID_BITS;
-};
-
-struct ltype_t
-{
- unsigned opcode : OPCODE_BITS;
- unsigned bigimm : BIGIMM_BITS;
- unsigned rd : XPRID_BITS;
-};
+#ifdef RISCV_ENABLE_RVC
+# define INSN_ALIGNMENT 2
+# define require_rvc
+#else
+# define INSN_ALIGNMENT 4
+# define require_rvc throw trap_illegal_instruction()
+#endif
-struct ftype_t
-{
- unsigned opcode : OPCODE_BITS;
- unsigned ffunct : FFUNCT_BITS;
- unsigned rm : RM_BITS;
- unsigned rs3 : FPRID_BITS;
- unsigned rs2 : FPRID_BITS;
- unsigned rs1 : FPRID_BITS;
- unsigned rd : FPRID_BITS;
-};
+#define insn_length(x) \
+ (((x) & 0x03) < 0x03 ? 2 : \
+ ((x) & 0x1f) < 0x1f ? 4 : \
+ ((x) & 0x3f) < 0x3f ? 6 : \
+ 8)
-union insn_t
+typedef uint64_t insn_bits_t;
+class insn_t
{
- itype_t itype;
- jtype_t jtype;
- rtype_t rtype;
- btype_t btype;
- ltype_t ltype;
- ftype_t ftype;
- uint32_t bits;
+public:
+ insn_t() = default;
+ insn_t(insn_bits_t bits) : b(bits) {}
+ insn_bits_t bits() { return b; }
+ int length() { return insn_length(b); }
+ int64_t i_imm() { return int64_t(b) >> 20; }
+ int64_t s_imm() { return x(7, 5) + (xs(25, 7) << 5); }
+ int64_t sb_imm() { return (x(8, 4) << 1) + (x(25,6) << 5) + (x(7,1) << 11) + (imm_sign() << 12); }
+ int64_t u_imm() { return int64_t(b) >> 12 << 12; }
+ int64_t uj_imm() { return (x(21, 10) << 1) + (x(20, 1) << 11) + (x(12, 8) << 12) + (imm_sign() << 20); }
+ uint64_t rd() { return x(7, 5); }
+ uint64_t rs1() { return x(15, 5); }
+ uint64_t rs2() { return x(20, 5); }
+ uint64_t rs3() { return x(27, 5); }
+ uint64_t rm() { return x(12, 3); }
+ uint64_t csr() { return x(20, 12); }
+
+ int64_t rvc_imm() { return x(2, 5) + (xs(12, 1) << 5); }
+ int64_t rvc_lwsp_imm() { return (x(4, 3) << 2) + (x(12, 1) << 5) + (x(2, 2) << 6); }
+ int64_t rvc_ldsp_imm() { return (x(5, 2) << 3) + (x(12, 1) << 5) + (x(2, 3) << 6); }
+ int64_t rvc_lw_imm() { return (x(5, 2) << 3) + (x(10, 1) << 6) + (x(11, 1) << 2) + (x(12, 1) << 5); }
+ int64_t rvc_ld_imm() { return (x(5, 2) << 3) + (x(10, 1) << 6) + (x(11, 1) << 7) + (x(12, 1) << 5); }
+ int64_t rvc_j_imm() { return (xs(2, 3) << 9) + (x(5, 2) << 3) + (x(7, 1) << 1) + (x(8, 2) << 7) + (x(10, 1) << 6) + (x(11, 1) << 2) + (x(12, 1) << 5); }
+ int64_t rvc_b_imm() { return (x(5, 2) << 3) + (x(7, 1) << 1) + (xs(8, 2) << 7) + (x(10, 1) << 6) + (x(11, 1) << 2) + (x(12, 1) << 5); }
+ uint64_t rvc_rd() { return rd(); }
+ uint64_t rvc_rs1() { return x(2, 5); }
+ uint64_t rvc_rs2() { return rd(); }
+ uint64_t rvc_rds() { return 8 + x(7, 3); }
+ uint64_t rvc_rs1s() { return 8 + x(2, 3); }
+ uint64_t rvc_rs2s() { return rvc_rds(); }
+private:
+ insn_bits_t b;
+ uint64_t x(int lo, int len) { return (b >> lo) & ((insn_bits_t(1) << len)-1); }
+ uint64_t xs(int lo, int len) { return int64_t(b) << (64-lo-len) >> (64-len); }
+ uint64_t imm_sign() { return xs(63, 1); }
};
-#include <stdio.h>
-class do_writeback
+template <class T, size_t N, bool zero_reg>
+class regfile_t
{
public:
- do_writeback(reg_t* _rf, int _rd) : rf(_rf), rd(_rd) {}
-
- const do_writeback& operator = (reg_t rhs)
+ void write(size_t i, T value)
{
-#if 0
- printf("R[%x] <= %llx\n",rd,(long long)rhs);
-#endif
- rf[rd] = rhs;
- rf[0] = 0;
- return *this;
+ if (!zero_reg || i != 0)
+ data[i] = value;
+ }
+ const T& operator [] (size_t i) const
+ {
+ return data[i];
}
-
- operator reg_t() { return rf[rd]; }
-
private:
- reg_t* rf;
- int rd;
+ T data[N];
};
-#define throw_illegal_instruction \
- ({ if (utmode) throw trap_vector_illegal_instruction; \
- else throw trap_illegal_instruction; })
-
// helpful macros, etc
-#define RS1 XPR[insn.rtype.rs1]
-#define RS2 XPR[insn.rtype.rs2]
-#define RD do_writeback(XPR,insn.rtype.rd)
-#define RA do_writeback(XPR,1)
-#define FRS1 FPR[insn.ftype.rs1]
-#define FRS2 FPR[insn.ftype.rs2]
-#define FRS3 FPR[insn.ftype.rs3]
-#define FRD FPR[insn.ftype.rd]
-#define BIGIMM insn.ltype.bigimm
-#define SIMM insn.itype.imm12
-#define BIMM ((signed)insn.btype.immlo | (insn.btype.immhi << IMMLO_BITS))
-#define SHAMT (insn.itype.imm12 & 0x3F)
-#define SHAMTW (insn.itype.imm12 & 0x1F)
-#define TARGET insn.jtype.target
-#define BRANCH_TARGET (pc + (BIMM << BRANCH_ALIGN_BITS))
-#define JUMP_TARGET (pc + (TARGET << JUMP_ALIGN_BITS))
-#define RM ({ int rm = insn.ftype.rm; \
- if(rm == 7) rm = (fsr & FSR_RD) >> FSR_RD_SHIFT; \
- if(rm > 4) throw_illegal_instruction; \
- rm; })
-
-#define require_supervisor if(unlikely(!(sr & SR_S))) throw trap_privileged_instruction
-#define xpr64 (xprlen == 64)
-#define require_xpr64 if(unlikely(!xpr64)) throw_illegal_instruction
-#define require_xpr32 if(unlikely(xpr64)) throw_illegal_instruction
-#define require_fp if(unlikely(!(sr & SR_EF))) throw trap_fp_disabled
-#define require_vector \
- ({ if(!(sr & SR_EV)) throw trap_vector_disabled; \
- else if (!utmode && (vecbanks_count < 3)) throw trap_vector_bank; \
- })
-#define cmp_trunc(reg) (reg_t(reg) << (64-xprlen))
-#define set_fp_exceptions ({ set_fsr(fsr | \
- (softfloat_exceptionFlags << FSR_AEXC_SHIFT)); \
- softfloat_exceptionFlags = 0; })
-
-#define sext32(x) ((sreg_t)(int32_t)(x))
-#define zext32(x) ((reg_t)(uint32_t)(x))
-#define sext_xprlen(x) ((sreg_t(x) << (64-xprlen)) >> (64-xprlen))
-#define zext_xprlen(x) ((reg_t(x) << (64-xprlen)) >> (64-xprlen))
+#define MMU (*p->get_mmu())
+#define STATE (*p->get_state())
+#define RS1 STATE.XPR[insn.rs1()]
+#define RS2 STATE.XPR[insn.rs2()]
+#define WRITE_REG(reg, value) STATE.XPR.write(reg, value)
+#define WRITE_RD(value) WRITE_REG(insn.rd(), value)
+
+#ifdef RISCV_ENABLE_COMMITLOG
+ #undef WRITE_REG
+ #define WRITE_REG(reg, value) ({ \
+ reg_t wdata = value; /* value is a func with side-effects */ \
+ STATE.log_reg_write = (commit_log_reg_t){reg << 1, wdata}; \
+ STATE.XPR.write(reg, wdata); \
+ })
+#endif
-#ifndef RISCV_ENABLE_RVC
-# define set_pc(x) \
- do { if((x) & (sizeof(insn_t)-1)) \
- { badvaddr = (x); throw trap_instruction_address_misaligned; } \
- npc = (x); \
- } while(0)
+// RVC macros
+#define WRITE_RVC_RDS(value) WRITE_REG(insn.rvc_rds(), value)
+#define RVC_RS1 STATE.XPR[insn.rvc_rs1()]
+#define RVC_RS2 STATE.XPR[insn.rvc_rs2()]
+#define RVC_RS1S STATE.XPR[insn.rvc_rs1s()]
+#define RVC_RS2S STATE.XPR[insn.rvc_rs2s()]
+#define RVC_SP STATE.XPR[2]
+
+// FPU macros
+#define FRS1 STATE.FPR[insn.rs1()]
+#define FRS2 STATE.FPR[insn.rs2()]
+#define FRS3 STATE.FPR[insn.rs3()]
+#define dirty_fp_state (STATE.mstatus |= MSTATUS_FS | (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD))
+#define dirty_ext_state (STATE.mstatus |= MSTATUS_XS | (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD))
+#define do_write_frd(value) (STATE.FPR.write(insn.rd(), value), dirty_fp_state)
+
+#ifndef RISCV_ENABLE_COMMITLOG
+# define WRITE_FRD(value) do_write_frd(value)
#else
-# define set_pc(x) \
- do { if((x) & ((sr & SR_EC) ? 1 : 3)) \
- { badvaddr = (x); throw trap_instruction_address_misaligned; } \
- npc = (x); \
- } while(0)
+# define WRITE_FRD(value) ({ \
+ freg_t wdata = (value); /* value may have side effects */ \
+ STATE.log_reg_write = (commit_log_reg_t){(insn.rd() << 1) | 1, wdata}; \
+ do_write_frd(wdata); \
+ })
#endif
+
+#define SHAMT (insn.i_imm() & 0x3F)
+#define BRANCH_TARGET (pc + insn.sb_imm())
+#define JUMP_TARGET (pc + insn.uj_imm())
+#define RM ({ int rm = insn.rm(); \
+ if(rm == 7) rm = STATE.frm; \
+ if(rm > 4) throw trap_illegal_instruction(); \
+ rm; })
-// RVC stuff
-
-#define INSN_IS_RVC(x) (((x) & 0x3) < 0x3)
-#define insn_length(x) (INSN_IS_RVC(x) ? 2 : 4)
-#define require_rvc if(!(sr & SR_EC)) throw_illegal_instruction
-
-#define CRD_REGNUM ((insn.bits >> 5) & 0x1f)
-#define CRD do_writeback(XPR, CRD_REGNUM)
-#define CRS1 XPR[(insn.bits >> 10) & 0x1f]
-#define CRS2 XPR[(insn.bits >> 5) & 0x1f]
-#define CIMM6 ((int32_t)((insn.bits >> 10) & 0x3f) << 26 >> 26)
-#define CIMM5U ((insn.bits >> 5) & 0x1f)
-#define CIMM5 ((int32_t)CIMM5U << 27 >> 27)
-#define CIMM10 ((int32_t)((insn.bits >> 5) & 0x3ff) << 22 >> 22)
-#define CBRANCH_TARGET (pc + (CIMM5 << BRANCH_ALIGN_BITS))
-#define CJUMP_TARGET (pc + (CIMM10 << JUMP_ALIGN_BITS))
-
-static const int rvc_rs1_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 7 };
-#define rvc_rd_regmap rvc_rs1_regmap
-#define rvc_rs2b_regmap rvc_rs1_regmap
-static const int rvc_rs2_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 0 };
-#define CRDS XPR[rvc_rd_regmap[(insn.bits >> 13) & 0x7]]
-#define FCRDS FPR[rvc_rd_regmap[(insn.bits >> 13) & 0x7]]
-#define CRS1S XPR[rvc_rs1_regmap[(insn.bits >> 10) & 0x7]]
-#define CRS2S XPR[rvc_rs2_regmap[(insn.bits >> 13) & 0x7]]
-#define CRS2BS XPR[rvc_rs2b_regmap[(insn.bits >> 5) & 0x7]]
-#define FCRS2S FPR[rvc_rs2_regmap[(insn.bits >> 13) & 0x7]]
-
-// vector stuff
-#define VL vl
+#define get_field(reg, mask) (((reg) & (decltype(reg))(mask)) / ((mask) & ~((mask) << 1)))
+#define set_field(reg, mask, val) (((reg) & ~(decltype(reg))(mask)) | (((decltype(reg))(val) * ((mask) & ~((mask) << 1))) & (decltype(reg))(mask)))
-#define UT_RS1(idx) uts[idx]->XPR[insn.rtype.rs1]
-#define UT_RS2(idx) uts[idx]->XPR[insn.rtype.rs2]
-#define UT_RD(idx) do_writeback(uts[idx]->XPR,insn.rtype.rd)
-#define UT_RA(idx) do_writeback(uts[idx]->XPR,1)
-#define UT_FRS1(idx) uts[idx]->FPR[insn.ftype.rs1]
-#define UT_FRS2(idx) uts[idx]->FPR[insn.ftype.rs2]
-#define UT_FRS3(idx) uts[idx]->FPR[insn.ftype.rs3]
-#define UT_FRD(idx) uts[idx]->FPR[insn.ftype.rd]
-#define UT_RM(idx) ((insn.ftype.rm != 7) ? insn.ftype.rm : \
- ((uts[idx]->fsr & FSR_RD) >> FSR_RD_SHIFT))
+#define require_privilege(p) if (get_field(STATE.mstatus, MSTATUS_PRV) < (p)) throw trap_illegal_instruction()
+#define require_rv64 if(unlikely(xlen != 64)) throw trap_illegal_instruction()
+#define require_rv32 if(unlikely(xlen != 32)) throw trap_illegal_instruction()
+#define require_fp if (unlikely((STATE.mstatus & MSTATUS_FS) == 0)) throw trap_illegal_instruction()
+#define require_accelerator if (unlikely((STATE.mstatus & MSTATUS_XS) == 0)) throw trap_illegal_instruction()
-#define UT_LOOP_START for (int i=0;i<VL; i++) {
-#define UT_LOOP_END }
-#define UT_LOOP_RS1 UT_RS1(i)
-#define UT_LOOP_RS2 UT_RS2(i)
-#define UT_LOOP_RD UT_RD(i)
-#define UT_LOOP_RA UT_RA(i)
-#define UT_LOOP_FRS1 UT_FRS1(i)
-#define UT_LOOP_FRS2 UT_FRS2(i)
-#define UT_LOOP_FRS3 UT_FRS3(i)
-#define UT_LOOP_FRD UT_FRD(i)
-#define UT_LOOP_RM UT_RM(i)
+#define cmp_trunc(reg) (reg_t(reg) << (64-xlen))
+#define set_fp_exceptions ({ STATE.fflags |= softfloat_exceptionFlags; \
+ softfloat_exceptionFlags = 0; })
-#define VEC_LOAD(dst, func, inc) \
- reg_t addr = RS1; \
- UT_LOOP_START \
- UT_LOOP_##dst = mmu.func(addr); \
- addr += inc; \
- UT_LOOP_END
+#define sext32(x) ((sreg_t)(int32_t)(x))
+#define zext32(x) ((reg_t)(uint32_t)(x))
+#define sext_xlen(x) (((sreg_t)(x) << (64-xlen)) >> (64-xlen))
+#define zext_xlen(x) (((reg_t)(x) << (64-xlen)) >> (64-xlen))
-#define VEC_STORE(src, func, inc) \
- reg_t addr = RS1; \
- UT_LOOP_START \
- mmu.func(addr, UT_LOOP_##src); \
- addr += inc; \
- UT_LOOP_END
+#define set_pc(x) \
+ do { if ((x) & (INSN_ALIGNMENT-1)) \
+ throw trap_instruction_address_misaligned(x); \
+ npc = sext_xlen(x); \
+ } while(0)
-enum vt_command_t
-{
- vt_command_stop,
-};
+#define PC_SERIALIZE 3 /* sentinel value indicating simulator pipeline flush */
+
+#define validate_csr(which, write) ({ \
+ if (!STATE.serialized) return PC_SERIALIZE; \
+ STATE.serialized = false; \
+ unsigned my_priv = get_field(STATE.mstatus, MSTATUS_PRV); \
+ unsigned csr_priv = get_field((which), 0x300); \
+ unsigned csr_read_only = get_field((which), 0xC00) == 3; \
+ if (((write) && csr_read_only) || my_priv < csr_priv) \
+ throw trap_illegal_instruction(); \
+ (which); })
#endif
projects / riscv-isa-sim.git / blobdiff