+// See LICENSE for license details.
+
#ifndef _RISCV_DECODE_H
#define _RISCV_DECODE_H
#define __STDC_LIMIT_MACROS
#include <stdint.h>
-
+#include <string.h>
+#include "pcr.h"
#include "config.h"
typedef int int128_t __attribute__((mode(TI)));
const int BRANCH_ALIGN_BITS = 1;
const int JUMP_ALIGN_BITS = 1;
-#define SR_ET 0x0000000000000001ULL
-#define SR_EF 0x0000000000000002ULL
-#define SR_EV 0x0000000000000004ULL
-#define SR_EC 0x0000000000000008ULL
-#define SR_PS 0x0000000000000010ULL
-#define SR_S 0x0000000000000020ULL
-#define SR_UX 0x0000000000000040ULL
-#define SR_SX 0x0000000000000080ULL
-#define SR_IM 0x000000000000FF00ULL
-#define SR_ZERO ~(SR_ET|SR_EF|SR_EV|SR_EC|SR_PS|SR_S|SR_UX|SR_SX|SR_IM)
-#define SR_IM_SHIFT 8
-#define TIMER_IRQ 7
-
-#define CAUSE_EXCCODE 0x000000FF
-#define CAUSE_IP 0x0000FF00
-#define CAUSE_EXCCODE_SHIFT 0
-#define CAUSE_IP_SHIFT 8
-
#define FP_RD_NE 0
#define FP_RD_0 1
#define FP_RD_DN 2
uint32_t bits;
};
-#if 0
-#include <stdio.h>
-class trace_writeback
+template <class T>
+class write_port_t
{
public:
- trace_writeback(reg_t* _rf, int _rd) : rf(_rf), rd(_rd) {}
-
- reg_t operator = (reg_t rhs)
+ write_port_t(T& _t) : t(_t) {}
+ T& operator = (const T& rhs)
{
- printf("R[%x] <= %llx\n",rd,(long long)rhs);
- rf[rd] = rhs;
- return rhs;
+ return t = rhs;
+ }
+ operator T()
+ {
+ return t;
+ }
+private:
+ T& t;
+};
+template <class T, size_t N, bool zero_reg>
+class regfile_t
+{
+public:
+ void reset()
+ {
+ memset(data, 0, sizeof(data));
+ }
+ write_port_t<T> write_port(size_t i)
+ {
+ return write_port_t<T>(data[i]);
+ }
+ const T& operator [] (size_t i) const
+ {
+ if (zero_reg)
+ const_cast<T&>(data[0]) = 0;
+ return data[i];
}
-
private:
- reg_t* rf;
- int rd;
+ T data[N];
};
-#define do_writeback(rf,rd) trace_writeback(rf,rd)
-#else
-#define do_writeback(rf,rd) rf[rd]
-#endif
+#define throw_illegal_instruction \
+ ({ if (utmode) throw trap_vector_illegal_instruction; \
+ else throw trap_illegal_instruction; })
// helpful macros, etc
#define RS1 XPR[insn.rtype.rs1]
#define RS2 XPR[insn.rtype.rs2]
-#define RD do_writeback(XPR,insn.rtype.rd)
-#define RA do_writeback(XPR,1)
+#define RD XPR.write_port(insn.rtype.rd)
+#define RA XPR.write_port(1)
#define FRS1 FPR[insn.ftype.rs1]
#define FRS2 FPR[insn.ftype.rs2]
#define FRS3 FPR[insn.ftype.rs3]
-#define FRD FPR[insn.ftype.rd]
+#define FRD FPR.write_port(insn.ftype.rd)
#define BIGIMM insn.ltype.bigimm
#define SIMM insn.itype.imm12
#define BIMM ((signed)insn.btype.immlo | (insn.btype.immhi << IMMLO_BITS))
#define TARGET insn.jtype.target
#define BRANCH_TARGET (pc + (BIMM << BRANCH_ALIGN_BITS))
#define JUMP_TARGET (pc + (TARGET << JUMP_ALIGN_BITS))
+#define ITYPE_EADDR sext_xprlen(RS1 + SIMM)
+#define BTYPE_EADDR sext_xprlen(RS1 + BIMM)
#define RM ({ int rm = insn.ftype.rm; \
if(rm == 7) rm = (fsr & FSR_RD) >> FSR_RD_SHIFT; \
- if(rm > 4) throw trap_illegal_instruction; \
+ if(rm > 4) throw_illegal_instruction; \
rm; })
-#define require_supervisor if(!(sr & SR_S)) throw trap_privileged_instruction
#define xpr64 (xprlen == 64)
-#define require_xpr64 if(!xpr64) throw trap_illegal_instruction
-#define require_xpr32 if(xpr64) throw trap_illegal_instruction
-#define require_fp if(!(sr & SR_EF)) throw trap_fp_disabled
-#define require_vector if(!(sr & SR_EV)) throw trap_vector_disabled
+
+#define require_supervisor if(unlikely(!(sr & SR_S))) throw trap_privileged_instruction
+#define require_xpr64 if(unlikely(!xpr64)) throw_illegal_instruction
+#define require_xpr32 if(unlikely(xpr64)) throw_illegal_instruction
+#ifndef RISCV_ENABLE_FPU
+# define require_fp throw trap_illegal_instruction
+#else
+# define require_fp if(unlikely(!(sr & SR_EF))) throw trap_fp_disabled
+#endif
+#ifndef RISCV_ENABLE_VEC
+# define require_vector throw trap_illegal_instruction
+#else
+# define require_vector \
+ ({ if(!(sr & SR_EV)) throw trap_vector_disabled; \
+ else if (!utmode && (vecbanks_count < 3)) throw trap_vector_bank; \
+ })
+#endif
+
#define cmp_trunc(reg) (reg_t(reg) << (64-xprlen))
#define set_fp_exceptions ({ set_fsr(fsr | \
(softfloat_exceptionFlags << FSR_AEXC_SHIFT)); \
softfloat_exceptionFlags = 0; })
-#define require_rvc if(!(sr & SR_EC)) throw trap_illegal_instruction
-#define insn_length(x) (((x).bits & 0x3) < 0x3 ? 2 : 4)
-
#define sext32(x) ((sreg_t)(int32_t)(x))
#define zext32(x) ((reg_t)(uint32_t)(x))
-#define sext_xprlen(x) ((sreg_t(x) << (64-xprlen)) >> (64-xprlen))
-#define zext_xprlen(x) ((reg_t(x) << (64-xprlen)) >> (64-xprlen))
+#define sext_xprlen(x) (((sreg_t)(x) << (64-xprlen)) >> (64-xprlen))
+#define zext_xprlen(x) (((reg_t)(x) << (64-xprlen)) >> (64-xprlen))
// RVC stuff
#define INSN_IS_RVC(x) (((x) & 0x3) < 0x3)
+#define insn_length(x) (INSN_IS_RVC(x) ? 2 : 4)
+#define require_rvc if(!(sr & SR_EC)) throw_illegal_instruction
-#define CRD do_writeback(XPR, (insn.bits >> 5) & 0x1f)
+#define CRD_REGNUM ((insn.bits >> 5) & 0x1f)
+#define CRD XPR.write_port(CRD_REGNUM)
#define CRS1 XPR[(insn.bits >> 10) & 0x1f]
#define CRS2 XPR[(insn.bits >> 5) & 0x1f]
#define CIMM6 ((int32_t)((insn.bits >> 10) & 0x3f) << 26 >> 26)
-#define CIMM5 ((int32_t)((insn.bits >> 5) & 0x1f) << 27 >> 27)
+#define CIMM5U ((insn.bits >> 5) & 0x1f)
+#define CIMM5 ((int32_t)CIMM5U << 27 >> 27)
#define CIMM10 ((int32_t)((insn.bits >> 5) & 0x3ff) << 22 >> 22)
+#define CBRANCH_TARGET (pc + (CIMM5 << BRANCH_ALIGN_BITS))
#define CJUMP_TARGET (pc + (CIMM10 << JUMP_ALIGN_BITS))
-static const uint8_t rvc_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 7 };
-#define CRDS do_writeback(XPR, rvc_regmap[(insn.bits >> 13) & 0x7])
-#define CRS1S XPR[rvc_regmap[(insn.bits >> 10) & 0x7]]
-#define CRS2S XPR[rvc_regmap[(insn.bits >> 13) & 0x7]]
+static const int rvc_rs1_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 7 };
+#define rvc_rd_regmap rvc_rs1_regmap
+#define rvc_rs2b_regmap rvc_rs1_regmap
+static const int rvc_rs2_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 0 };
+#define CRDS XPR.write_port(rvc_rd_regmap[(insn.bits >> 13) & 0x7])
+#define FCRDS FPR.write_port(rvc_rd_regmap[(insn.bits >> 13) & 0x7])
+#define CRS1S XPR[rvc_rs1_regmap[(insn.bits >> 10) & 0x7]]
+#define CRS2S XPR[rvc_rs2_regmap[(insn.bits >> 13) & 0x7]]
+#define CRS2BS XPR[rvc_rs2b_regmap[(insn.bits >> 5) & 0x7]]
+#define FCRS2S FPR[rvc_rs2_regmap[(insn.bits >> 13) & 0x7]]
// vector stuff
#define VL vl
#define UT_RS1(idx) uts[idx]->XPR[insn.rtype.rs1]
#define UT_RS2(idx) uts[idx]->XPR[insn.rtype.rs2]
-#define UT_RD(idx) do_writeback(uts[idx]->XPR,insn.rtype.rd)
-#define UT_RA(idx) do_writeback(uts[idx]->XPR,1)
+#define UT_RD(idx) uts[idx]->XPR.write_port(insn.rtype.rd)
+#define UT_RA(idx) uts[idx]->XPR.write_port(1)
#define UT_FRS1(idx) uts[idx]->FPR[insn.ftype.rs1]
#define UT_FRS2(idx) uts[idx]->FPR[insn.ftype.rs2]
#define UT_FRS3(idx) uts[idx]->FPR[insn.ftype.rs3]
-#define UT_FRD(idx) uts[idx]->FPR[insn.ftype.rd]
+#define UT_FRD(idx) uts[idx]->FPR.write_port(insn.ftype.rd)
#define UT_RM(idx) ((insn.ftype.rm != 7) ? insn.ftype.rm : \
((uts[idx]->fsr & FSR_RD) >> FSR_RD_SHIFT))
projects / riscv-isa-sim.git / blobdiff