Commit log now prints while interrupts are enabled.

[riscv-isa-sim.git] / riscv / decode.h

diff --git a/riscv/decode.h b/riscv/decode.h
index 2229afbf6823d9bd7fabe3becfff44e30714be94..ce57c772ffbf4c6073d52dda056098bf31ab9598 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -52,20 +52,22 @@ class insn_t
 {
 public:
   uint32_t bits() { return b; }
-  reg_t i_imm() { return int64_t(int32_t(b) >> 20); }
-  reg_t s_imm() { return x(7, 5) | (x(25, 7) << 5) | (imm_sign() << 12); }
-  reg_t sb_imm() { return (x(8, 4) << 1) | (x(25,6) << 5) | (x(7,1) << 11) | (imm_sign() << 12); }
-  reg_t u_imm() { return int64_t(int32_t(b) >> 12 << 12); }
-  reg_t uj_imm() { return (x(21, 10) << 1) | (x(20, 1) << 11) | (x(12, 8) << 12) | (imm_sign() << 20); }
+  int32_t i_imm() { return int32_t(b) >> 20; }
+  int32_t s_imm() { return x(7, 5) + (xs(25, 7) << 5); }
+  int32_t sb_imm() { return (x(8, 4) << 1) + (x(25,6) << 5) + (x(7,1) << 11) + (imm_sign() << 12); }
+  int32_t u_imm() { return int32_t(b) >> 12 << 12; }
+  int32_t uj_imm() { return (x(21, 10) << 1) + (x(20, 1) << 11) + (x(12, 8) << 12) + (imm_sign() << 20); }
   uint32_t rd() { return x(7, 5); }
   uint32_t rs1() { return x(15, 5); }
   uint32_t rs2() { return x(20, 5); }
   uint32_t rs3() { return x(27, 5); }
   uint32_t rm() { return x(12, 3); }
+  uint32_t csr() { return x(20, 12); }
 private:
   uint32_t b;
-  reg_t x(int lo, int len) { return b << (32-lo-len) >> (32-len); }
-  reg_t imm_sign() { return int64_t(int32_t(b) >> 31); }
+  uint32_t x(int lo, int len) { return b << (32-lo-len) >> (32-len); }
+  uint32_t xs(int lo, int len) { return int32_t(b) << (32-lo-len) >> (32-len); }
+  uint32_t imm_sign() { return xs(31, 1); }
 };
 
 template <class T, size_t N, bool zero_reg>
@@ -79,11 +81,11 @@ public:
   void write(size_t i, T value)
   {
     data[i] = value;
+    if (zero_reg)
+      data[0] = 0;
   }
   const T& operator [] (size_t i) const
   {
-    if (zero_reg)
-      const_cast<T&>(data[0]) = 0;
     return data[i];
   }
 private:
@@ -99,10 +101,8 @@ private:
 #ifdef RISCV_ENABLE_COMMITLOG
   #undef WRITE_RD 
   #define WRITE_RD(value) ({ \
-        bool in_spvr = p->get_state()->sr & SR_S; \
         reg_t wdata = value; /* value is a func with side-effects */ \
-        if (!in_spvr) \
-          fprintf(stderr, "x%u 0x%016" PRIx64, insn.rd(), ((uint64_t) wdata)); \
+        p->get_state()->log_reg_write = (commit_log_reg_t){insn.rd() << 1, wdata}; \
         p->get_state()->XPR.write(insn.rd(), wdata); \
       })
 #endif
@@ -115,10 +115,8 @@ private:
 #ifdef RISCV_ENABLE_COMMITLOG
   #undef WRITE_FRD 
   #define WRITE_FRD(value) ({ \
-        bool in_spvr = p->get_state()->sr & SR_S; \
         freg_t wdata = value; /* value is a func with side-effects */ \
-        if (!in_spvr) \
-          fprintf(stderr, "f%u 0x%016" PRIx64, insn.rd(), ((uint64_t) wdata)); \
+        p->get_state()->log_reg_write = (commit_log_reg_t){(insn.rd() << 1) | 1, wdata}; \
         p->get_state()->FPR.write(insn.rd(), wdata); \
       })
 #endif
@@ -163,13 +161,16 @@ private:
 #define set_pc(x) \
   do { if ((x) & 3 /* For now... */) \
          throw trap_instruction_address_misaligned(); \
-       npc = (x); \
+       npc = sext_xprlen(x); \
      } while(0)
 
 #define validate_csr(which, write) ({ \
-  int read_priv = ((which) >> 10) & 3; \
-  int write_priv = ((which) >> 8) & 3; \
-  if (read_priv > 0 || (write_priv > 0 && (write))) require_supervisor; \
+  unsigned my_priv = (p->get_state()->sr & SR_S) ? 1 : 0; \
+  unsigned read_priv = ((which) >> 10) & 3; \
+  unsigned write_priv = (((which) >> 8) & 3); \
+  if (read_priv == 3) read_priv = write_priv, write_priv = -1; \
+  if (my_priv < ((write) ? write_priv : read_priv)) \
+    throw trap_privileged_instruction(); \
   (which); })
 
 #endif