#ifndef _RISCV_DECODE_H
#define _RISCV_DECODE_H
+#if (-1 != ~0) || ((-1 >> 1) != -1)
+# error spike requires a two''s-complement c++ implementation
+#endif
+
#define __STDC_LIMIT_MACROS
#include <stdint.h>
#include <string.h>
-#include "pcr.h"
+#include "encoding.h"
#include "config.h"
#include "common.h"
+#include <cinttypes>
typedef int int128_t __attribute__((mode(TI)));
typedef unsigned int uint128_t __attribute__((mode(TI)));
typedef uint64_t reg_t;
typedef uint64_t freg_t;
-const int OPCODE_BITS = 7;
-
-const int XPRID_BITS = 5;
-const int NXPR = 1 << XPRID_BITS;
-
-const int FPR_BITS = 64;
-const int FPRID_BITS = 5;
-const int NFPR = 1 << FPRID_BITS;
-
-const int IMM_BITS = 12;
-const int IMMLO_BITS = 7;
-const int TARGET_BITS = 25;
-const int FUNCT_BITS = 3;
-const int FUNCTR_BITS = 7;
-const int FFUNCT_BITS = 2;
-const int RM_BITS = 3;
-const int BIGIMM_BITS = 20;
-const int BRANCH_ALIGN_BITS = 1;
-const int JUMP_ALIGN_BITS = 1;
+const int NXPR = 32;
+const int NFPR = 32;
#define FP_RD_NE 0
#define FP_RD_0 1
#define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT)
#define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
-#define FSR_ZERO ~(FSR_RD | FSR_AEXC)
-
-// note: bit fields are in little-endian order
-struct itype_t
-{
- unsigned opcode : OPCODE_BITS;
- unsigned funct : FUNCT_BITS;
- signed imm12 : IMM_BITS;
- unsigned rs1 : XPRID_BITS;
- unsigned rd : XPRID_BITS;
-};
-
-struct btype_t
-{
- unsigned opcode : OPCODE_BITS;
- unsigned funct : FUNCT_BITS;
- unsigned immlo : IMMLO_BITS;
- unsigned rs2 : XPRID_BITS;
- unsigned rs1 : XPRID_BITS;
- signed immhi : IMM_BITS-IMMLO_BITS;
-};
-
-struct rtype_t
-{
- unsigned opcode : OPCODE_BITS;
- unsigned funct : FUNCT_BITS;
- unsigned functr : FUNCTR_BITS;
- unsigned rs2 : XPRID_BITS;
- unsigned rs1 : XPRID_BITS;
- unsigned rd : XPRID_BITS;
-};
-
-struct ltype_t
-{
- unsigned opcode : OPCODE_BITS;
- signed bigimm : BIGIMM_BITS;
- unsigned rd : XPRID_BITS;
-};
-
-struct ftype_t
-{
- unsigned opcode : OPCODE_BITS;
- unsigned ffunct : FFUNCT_BITS;
- unsigned rm : RM_BITS;
- unsigned rs3 : FPRID_BITS;
- unsigned rs2 : FPRID_BITS;
- unsigned rs1 : FPRID_BITS;
- unsigned rd : FPRID_BITS;
-};
-
-union insn_t
-{
- itype_t itype;
- rtype_t rtype;
- btype_t btype;
- ltype_t ltype;
- ftype_t ftype;
- uint_fast32_t bits;
-};
-
-template <class T>
-class write_port_t
+class insn_t
{
public:
- write_port_t(T& _t) : t(_t) {}
- T& operator = (const T& rhs)
- {
- return t = rhs;
- }
- operator T()
- {
- return t;
- }
+ uint32_t bits() { return b; }
+ int32_t i_imm() { return int32_t(b) >> 20; }
+ int32_t s_imm() { return x(7, 5) + (xs(25, 7) << 5); }
+ int32_t sb_imm() { return (x(8, 4) << 1) + (x(25,6) << 5) + (x(7,1) << 11) + (imm_sign() << 12); }
+ int32_t u_imm() { return int32_t(b) >> 12 << 12; }
+ int32_t uj_imm() { return (x(21, 10) << 1) + (x(20, 1) << 11) + (x(12, 8) << 12) + (imm_sign() << 20); }
+ uint32_t rd() { return x(7, 5); }
+ uint32_t rs1() { return x(15, 5); }
+ uint32_t rs2() { return x(20, 5); }
+ uint32_t rs3() { return x(27, 5); }
+ uint32_t rm() { return x(12, 3); }
+ uint32_t csr() { return x(20, 12); }
private:
- T& t;
+ uint32_t b;
+ uint32_t x(int lo, int len) { return b << (32-lo-len) >> (32-len); }
+ uint32_t xs(int lo, int len) { return int32_t(b) << (32-lo-len) >> (32-len); }
+ uint32_t imm_sign() { return xs(31, 1); }
};
+
template <class T, size_t N, bool zero_reg>
class regfile_t
{
{
memset(data, 0, sizeof(data));
}
- write_port_t<T> write_port(size_t i)
+ void write(size_t i, T value)
{
+ data[i] = value;
if (zero_reg)
- const_cast<T&>(data[0]) = 0;
- return write_port_t<T>(data[i]);
+ data[0] = 0;
}
const T& operator [] (size_t i) const
{
- if (zero_reg)
- const_cast<T&>(data[0]) = 0;
return data[i];
}
private:
// helpful macros, etc
#define MMU (*p->get_mmu())
-#define RS1 p->get_state()->XPR[insn.rtype.rs1]
-#define RS2 p->get_state()->XPR[insn.rtype.rs2]
-#define RD p->get_state()->XPR.write_port(insn.rtype.rd)
-#define FRS1 p->get_state()->FPR[insn.ftype.rs1]
-#define FRS2 p->get_state()->FPR[insn.ftype.rs2]
-#define FRS3 p->get_state()->FPR[insn.ftype.rs3]
-#define FRD p->get_state()->FPR.write_port(insn.ftype.rd)
-#define BIGIMM insn.ltype.bigimm
-#define SIMM insn.itype.imm12
-#define BIMM ((signed)insn.btype.immlo | (insn.btype.immhi << IMMLO_BITS))
-#define SHAMT (insn.itype.imm12 & 0x3F)
-#define SHAMTW (insn.itype.imm12 & 0x1F)
-#define BRANCH_TARGET (pc + (BIMM << BRANCH_ALIGN_BITS))
-#define JUMP_TARGET (pc + (BIGIMM << JUMP_ALIGN_BITS))
-#define ITYPE_EADDR sext_xprlen(RS1 + SIMM)
-#define BTYPE_EADDR sext_xprlen(RS1 + BIMM)
-#define RM ({ int rm = insn.ftype.rm; \
- if(rm == 7) rm = (p->get_state()->fsr & FSR_RD) >> FSR_RD_SHIFT; \
+#define RS1 p->get_state()->XPR[insn.rs1()]
+#define RS2 p->get_state()->XPR[insn.rs2()]
+#define WRITE_RD(value) p->get_state()->XPR.write(insn.rd(), value)
+
+#ifdef RISCV_ENABLE_COMMITLOG
+ #undef WRITE_RD
+ #define WRITE_RD(value) ({ \
+ reg_t wdata = value; /* value is a func with side-effects */ \
+ p->get_state()->log_reg_write = (commit_log_reg_t){insn.rd() << 1, wdata}; \
+ p->get_state()->XPR.write(insn.rd(), wdata); \
+ })
+#endif
+
+#define FRS1 p->get_state()->FPR[insn.rs1()]
+#define FRS2 p->get_state()->FPR[insn.rs2()]
+#define FRS3 p->get_state()->FPR[insn.rs3()]
+#define WRITE_FRD(value) p->get_state()->FPR.write(insn.rd(), value)
+
+#ifdef RISCV_ENABLE_COMMITLOG
+ #undef WRITE_FRD
+ #define WRITE_FRD(value) ({ \
+ freg_t wdata = value; /* value is a func with side-effects */ \
+ p->get_state()->log_reg_write = (commit_log_reg_t){(insn.rd() << 1) | 1, wdata}; \
+ p->get_state()->FPR.write(insn.rd(), wdata); \
+ })
+#endif
+
+
+
+#define SHAMT (insn.i_imm() & 0x3F)
+#define BRANCH_TARGET (pc + insn.sb_imm())
+#define JUMP_TARGET (pc + insn.uj_imm())
+#define RM ({ int rm = insn.rm(); \
+ if(rm == 7) rm = p->get_state()->frm; \
if(rm > 4) throw trap_illegal_instruction(); \
rm; })
#else
# define require_fp if(unlikely(!(p->get_state()->sr & SR_EF))) throw trap_fp_disabled()
#endif
+#define require_accelerator if(unlikely(!(p->get_state()->sr & SR_EA))) throw trap_accelerator_disabled()
#define cmp_trunc(reg) (reg_t(reg) << (64-xprlen))
-#define set_fp_exceptions ({ p->set_fsr(p->get_state()->fsr | \
- (softfloat_exceptionFlags << FSR_AEXC_SHIFT)); \
+#define set_fp_exceptions ({ p->get_state()->fflags |= softfloat_exceptionFlags; \
softfloat_exceptionFlags = 0; })
#define sext32(x) ((sreg_t)(int32_t)(x))
#define set_pc(x) \
do { if ((x) & 3 /* For now... */) \
throw trap_instruction_address_misaligned(); \
- npc = (x); \
+ npc = sext_xprlen(x); \
} while(0)
+#define validate_csr(which, write) ({ \
+ unsigned my_priv = (p->get_state()->sr & SR_S) ? 1 : 0; \
+ unsigned read_priv = ((which) >> 10) & 3; \
+ unsigned write_priv = (((which) >> 8) & 3); \
+ if (read_priv == 3) read_priv = write_priv, write_priv = -1; \
+ if (my_priv < ((write) ? write_priv : read_priv)) \
+ throw trap_privileged_instruction(); \
+ (which); })
+
#endif
projects / riscv-isa-sim.git / blobdiff