Commit log now prints while interrupts are enabled.

[riscv-isa-sim.git] / riscv / decode.h

diff --git a/riscv/decode.h b/riscv/decode.h
index 3d20b62735e175991207a594d18674a7a8a31315..ce57c772ffbf4c6073d52dda056098bf31ab9598 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -10,9 +10,10 @@
 #define __STDC_LIMIT_MACROS
 #include <stdint.h>
 #include <string.h>
-#include "pcr.h"
+#include "encoding.h"
 #include "config.h"
 #include "common.h"
+#include <cinttypes>
 
 typedef int int128_t __attribute__((mode(TI)));
 typedef unsigned int uint128_t __attribute__((mode(TI)));
@@ -47,44 +48,28 @@ const int NFPR = 32;
 #define FSR_NXA  (FPEXC_NX << FSR_AEXC_SHIFT)
 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
 
-#define FSR_ZERO ~(FSR_RD | FSR_AEXC)
-
 class insn_t
 {
 public:
   uint32_t bits() { return b; }
-  reg_t i_imm() { return int64_t(int32_t(b) >> 20); }
-  reg_t s_imm() { return x(7, 5) | (x(25, 7) << 5) | (imm_sign() << 12); }
-  reg_t sb_imm() { return (x(8, 4) << 1) | (x(25,6) << 5) | (x(7,1) << 11) | (imm_sign() << 12); }
-  reg_t u_imm() { return int64_t(int32_t(b) >> 12 << 12); }
-  reg_t uj_imm() { return (x(21, 10) << 1) | (x(20, 1) << 11) | (x(12, 8) << 12) | (imm_sign() << 20); }
+  int32_t i_imm() { return int32_t(b) >> 20; }
+  int32_t s_imm() { return x(7, 5) + (xs(25, 7) << 5); }
+  int32_t sb_imm() { return (x(8, 4) << 1) + (x(25,6) << 5) + (x(7,1) << 11) + (imm_sign() << 12); }
+  int32_t u_imm() { return int32_t(b) >> 12 << 12; }
+  int32_t uj_imm() { return (x(21, 10) << 1) + (x(20, 1) << 11) + (x(12, 8) << 12) + (imm_sign() << 20); }
   uint32_t rd() { return x(7, 5); }
   uint32_t rs1() { return x(15, 5); }
   uint32_t rs2() { return x(20, 5); }
   uint32_t rs3() { return x(27, 5); }
   uint32_t rm() { return x(12, 3); }
+  uint32_t csr() { return x(20, 12); }
 private:
   uint32_t b;
-  reg_t x(int lo, int len) { return b << (32-lo-len) >> (32-len); }
-  reg_t imm_sign() { return int64_t(int32_t(b) >> 31); }
+  uint32_t x(int lo, int len) { return b << (32-lo-len) >> (32-len); }
+  uint32_t xs(int lo, int len) { return int32_t(b) << (32-lo-len) >> (32-len); }
+  uint32_t imm_sign() { return xs(31, 1); }
 };
 
-template <class T>
-class write_port_t
-{
-public:
-  write_port_t(T& _t) : t(_t) {}
-  T& operator = (const T& rhs)
-  {
-    return t = rhs;
-  }
-  operator T()
-  {
-    return t;
-  }
-private:
-  T& t;
-};
 template <class T, size_t N, bool zero_reg>
 class regfile_t
 {
@@ -93,16 +78,14 @@ public:
   {
     memset(data, 0, sizeof(data));
   }
-  write_port_t<T> write_port(size_t i)
+  void write(size_t i, T value)
   {
+    data[i] = value;
     if (zero_reg)
-      const_cast<T&>(data[0]) = 0;
-    return write_port_t<T>(data[i]);
+      data[0] = 0;
   }
   const T& operator [] (size_t i) const
   {
-    if (zero_reg)
-      const_cast<T&>(data[0]) = 0;
     return data[i];
   }
 private:
@@ -113,16 +96,38 @@ private:
 #define MMU (*p->get_mmu())
 #define RS1 p->get_state()->XPR[insn.rs1()]
 #define RS2 p->get_state()->XPR[insn.rs2()]
-#define RD p->get_state()->XPR.write_port(insn.rd())
+#define WRITE_RD(value) p->get_state()->XPR.write(insn.rd(), value)
+
+#ifdef RISCV_ENABLE_COMMITLOG
+  #undef WRITE_RD 
+  #define WRITE_RD(value) ({ \
+        reg_t wdata = value; /* value is a func with side-effects */ \
+        p->get_state()->log_reg_write = (commit_log_reg_t){insn.rd() << 1, wdata}; \
+        p->get_state()->XPR.write(insn.rd(), wdata); \
+      })
+#endif
+
 #define FRS1 p->get_state()->FPR[insn.rs1()]
 #define FRS2 p->get_state()->FPR[insn.rs2()]
 #define FRS3 p->get_state()->FPR[insn.rs3()]
-#define FRD p->get_state()->FPR.write_port(insn.rd())
+#define WRITE_FRD(value) p->get_state()->FPR.write(insn.rd(), value)
+ 
+#ifdef RISCV_ENABLE_COMMITLOG
+  #undef WRITE_FRD 
+  #define WRITE_FRD(value) ({ \
+        freg_t wdata = value; /* value is a func with side-effects */ \
+        p->get_state()->log_reg_write = (commit_log_reg_t){(insn.rd() << 1) | 1, wdata}; \
+        p->get_state()->FPR.write(insn.rd(), wdata); \
+      })
+#endif
+ 
+
+
 #define SHAMT (insn.i_imm() & 0x3F)
 #define BRANCH_TARGET (pc + insn.sb_imm())
 #define JUMP_TARGET (pc + insn.uj_imm())
 #define RM ({ int rm = insn.rm(); \
-              if(rm == 7) rm = (p->get_state()->fsr & FSR_RD) >> FSR_RD_SHIFT; \
+              if(rm == 7) rm = p->get_state()->frm; \
               if(rm > 4) throw trap_illegal_instruction(); \
               rm; })
 
@@ -136,10 +141,10 @@ private:
 #else
 # define require_fp if(unlikely(!(p->get_state()->sr & SR_EF))) throw trap_fp_disabled()
 #endif
+#define require_accelerator if(unlikely(!(p->get_state()->sr & SR_EA))) throw trap_accelerator_disabled()
 
 #define cmp_trunc(reg) (reg_t(reg) << (64-xprlen))
-#define set_fp_exceptions ({ p->set_fsr(p->get_state()->fsr | \
-                               (softfloat_exceptionFlags << FSR_AEXC_SHIFT)); \
+#define set_fp_exceptions ({ p->get_state()->fflags |= softfloat_exceptionFlags; \
                              softfloat_exceptionFlags = 0; })
 
 #define sext32(x) ((sreg_t)(int32_t)(x))
@@ -156,7 +161,16 @@ private:
 #define set_pc(x) \
   do { if ((x) & 3 /* For now... */) \
          throw trap_instruction_address_misaligned(); \
-       npc = (x); \
+       npc = sext_xprlen(x); \
      } while(0)
 
+#define validate_csr(which, write) ({ \
+  unsigned my_priv = (p->get_state()->sr & SR_S) ? 1 : 0; \
+  unsigned read_priv = ((which) >> 10) & 3; \
+  unsigned write_priv = (((which) >> 8) & 3); \
+  if (read_priv == 3) read_priv = write_priv, write_priv = -1; \
+  if (my_priv < ((write) ? write_priv : read_priv)) \
+    throw trap_privileged_instruction(); \
+  (which); })
+
 #endif