add load-reserved/store-conditional instructions

[riscv-isa-sim.git] / riscv / disasm.cc

diff --git a/riscv/disasm.cc b/riscv/disasm.cc
index c59a5dad7a0d95336771ad85ac39aa014115892a..d8c4ab0b79afc721fc8c4d426b49c8a34cb8a1f2 100644 (file)
--- a/riscv/disasm.cc
+++ b/riscv/disasm.cc
@@ -475,6 +475,11 @@ disassembler::disassembler()
   DEFINE_XAMO(amominu_d)
   DEFINE_XAMO(amomaxu_d)
 
+  DEFINE_XAMO(lr_w)
+  DEFINE_XAMO(sc_w)
+  DEFINE_XAMO(lr_d)
+  DEFINE_XAMO(sc_d)
+
   DEFINE_FLOAD(flw)
   DEFINE_FLOAD(fld)