Fix histogram for RVC

[riscv-isa-sim.git] / riscv / execute.cc

diff --git a/riscv/execute.cc b/riscv/execute.cc
index 249d6aefe0eb22ba6efeb8fe0e720387a38ed8f4..4711b49b958b2b1e545b7ba59b9b2326306084ea 100644 (file)
--- a/riscv/execute.cc
+++ b/riscv/execute.cc
@@ -32,11 +32,10 @@ static void commit_log_print_insn(state_t* state, reg_t pc, insn_t insn)
 #endif
 }
 
-inline void processor_t::update_histogram(size_t pc)
+inline void processor_t::update_histogram(reg_t pc)
 {
 #ifdef RISCV_ENABLE_HISTOGRAM
-  size_t idx = pc >> 2;
-  pc_histogram[idx]++;
+  pc_histogram[pc]++;
 #endif
 }