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Implement clearing-misa.C-while-PC-is-misaligned proposal
[riscv-isa-sim.git]
/
riscv
/
execute.cc
diff --git
a/riscv/execute.cc
b/riscv/execute.cc
index e60ffd117ebeb58a0f8f16c46bb5161ce1d58053..c5cafc2ee5ead5df9b35f2156540f288167a3ec5 100644
(file)
--- a/
riscv/execute.cc
+++ b/
riscv/execute.cc
@@
-114,6
+114,7
@@
void processor_t::step(size_t n)
default: abort(); \
} \
pc = state.pc; \
+ check_pc_alignment(pc); \
break; \
} else { \
state.pc = pc; \